from nmigen import Module, Signal
-from nmigen.back.pysim import Simulator, Delay, Settle
+from nmigen.sim import Simulator, Delay, Settle
from nmutil.formaltest import FHDLTestCase
import unittest
-from soc.decoder.isa.caller import ISACaller
-from soc.decoder.power_decoder import (create_pdecode)
-from soc.decoder.power_decoder2 import (PowerDecode2)
-from soc.simulator.program import Program
-from soc.decoder.isa.caller import ISACaller, SVP64State
-from soc.decoder.selectable_int import SelectableInt
-from soc.decoder.orderedset import OrderedSet
-from soc.decoder.isa.all import ISA
-from soc.decoder.isa.test_caller import Register, run_tst
-from soc.sv.trans.svp64 import SVP64Asm
-from soc.consts import SVP64CROffs
+from openpower.decoder.isa.caller import ISACaller
+from openpower.decoder.power_decoder import (create_pdecode)
+from openpower.decoder.power_decoder2 import (PowerDecode2)
+from openpower.simulator.program import Program
+from openpower.decoder.isa.caller import ISACaller, SVP64State, CRFields
+from openpower.decoder.selectable_int import SelectableInt
+from openpower.decoder.orderedset import OrderedSet
+from openpower.decoder.isa.all import ISA
+from openpower.decoder.isa.test_caller import Register, run_tst
+from openpower.sv.trans.svp64 import SVP64Asm
+from openpower.consts import SVP64CROffs
from copy import deepcopy
class DecoderTestCase(FHDLTestCase):
"addi 2, 0, 0x0008",
"addi 5, 0, 0x1234",
"addi 6, 0, 0x1235",
- "sv.stw 5.v, 0(1.v)",
- "sv.lwz 9.v, 0(1.v)"])
+ "sv.stw *5, 0(*1)",
+ "sv.lwz *9, 0(*1)"])
lst = list(lst)
# SVSTATE (in this case, VL=2)
svstate = SVP64State()
- svstate.vl[0:7] = 2 # VL
- svstate.maxvl[0:7] = 2 # MAXVL
- print ("SVSTATE", bin(svstate.spr.asint()))
+ svstate.vl = 2 # VL
+ svstate.maxvl = 2 # MAXVL
+ print ("SVSTATE", bin(svstate.asint()))
with Program(lst, bigendian=False) as program:
sim = self.run_tst_program(program, svstate=svstate)
# |
# dest r3=0b10 N Y
- isa = SVP64Asm(['sv.extsb/sm=~r3/dm=r3 5.v, 9.v'
+ isa = SVP64Asm(['sv.extsb/sm=~r3/dm=r3 *5, *9'
])
lst = list(isa)
print ("listing", lst)
initial_regs[10] = 0x90 # this gets skipped
# SVSTATE (in this case, VL=2)
svstate = SVP64State()
- svstate.vl[0:7] = 2 # VL
- svstate.maxvl[0:7] = 2 # MAXVL
- print ("SVSTATE", bin(svstate.spr.asint()))
+ svstate.vl = 2 # VL
+ svstate.maxvl = 2 # MAXVL
+ print ("SVSTATE", bin(svstate.asint()))
# copy before running
expected_regs = deepcopy(initial_regs)
expected_regs[5] = 0x0 # dest r3 is 0b10: skip
def test_sv_extsw_intpred_dz(self):
# extsb, integer twin-pred mask: dest is r3 (0b01), zeroing on dest
- isa = SVP64Asm(['sv.extsb/dm=r3/dz 5.v, 9.v'
+ isa = SVP64Asm(['sv.extsb/dm=r3/dz *5, *9'
])
lst = list(isa)
print ("listing", lst)
initial_regs[10] = 0x90 # this gets read but the output gets zero'd
# SVSTATE (in this case, VL=2)
svstate = SVP64State()
- svstate.vl[0:7] = 2 # VL
- svstate.maxvl[0:7] = 2 # MAXVL
- print ("SVSTATE", bin(svstate.spr.asint()))
+ svstate.vl = 2 # VL
+ svstate.maxvl = 2 # MAXVL
+ print ("SVSTATE", bin(svstate.asint()))
# copy before running
expected_regs = deepcopy(initial_regs)
expected_regs[5] = 0xffff_ffff_ffff_ff91 # dest r3 is 0b01: store
# adds, integer predicated mask r3=0b10
# 1 = 5 + 9 => not to be touched (skipped)
# 2 = 6 + 10 => 0x3334 = 0x2223+0x1111
- isa = SVP64Asm(['sv.add/m=r3 1.v, 5.v, 9.v'
+ # reg num 0 1 2 3 4 5 6 7 8 9 10 11
+ # src r3=0b10 N Y N Y
+ # | | | |
+ # +-------+ | add + |
+ # | +-------+ add --+
+ # | |
+ # dest r3=0b10 N Y
+ isa = SVP64Asm(['sv.add/m=r3 *1, *5, *9'
])
lst = list(isa)
print ("listing", lst)
initial_regs[6] = 0x2223
# SVSTATE (in this case, VL=2)
svstate = SVP64State()
- svstate.vl[0:7] = 2 # VL
- svstate.maxvl[0:7] = 2 # MAXVL
- print ("SVSTATE", bin(svstate.spr.asint()))
+ svstate.vl = 2 # VL
+ svstate.maxvl = 2 # MAXVL
+ print ("SVSTATE", bin(svstate.asint()))
# copy before running
expected_regs = deepcopy(initial_regs)
expected_regs[1] = 0xbeef
# adds, CR predicated mask CR4.eq = 1, CR5.eq = 0, invert (ne)
# 1 = 5 + 9 => not to be touched (skipped)
# 2 = 6 + 10 => 0x3334 = 0x2223+0x1111
- isa = SVP64Asm(['sv.add/m=ne 1.v, 5.v, 9.v'
+ isa = SVP64Asm(['sv.add/m=ne *1, *5, *9'
])
lst = list(isa)
print ("listing", lst)
initial_regs[6] = 0x2223
# SVSTATE (in this case, VL=2)
svstate = SVP64State()
- svstate.vl[0:7] = 2 # VL
- svstate.maxvl[0:7] = 2 # MAXVL
- print ("SVSTATE", bin(svstate.spr.asint()))
+ svstate.vl = 2 # VL
+ svstate.maxvl = 2 # MAXVL
+ print ("SVSTATE", bin(svstate.asint()))
# copy before running
expected_regs = deepcopy(initial_regs)
expected_regs[1] = 0xbeef
initial_cr=cr)
self._check_regs(sim, expected_regs)
- def tst_sv_add_2(self):
- # adds:
- # 1 = 5 + 9 => 0x5555 = 0x4321+0x1234
- # r1 is scalar so ENDS EARLY
- isa = SVP64Asm(['sv.add 1, 5.v, 9.v'
- ])
- lst = list(isa)
- print ("listing", lst)
-
- # initial values in GPR regfile
- initial_regs = [0] * 32
- initial_regs[9] = 0x1234
- initial_regs[10] = 0x1111
- initial_regs[5] = 0x4321
- initial_regs[6] = 0x2223
- # SVSTATE (in this case, VL=2)
- svstate = SVP64State()
- svstate.vl[0:7] = 2 # VL
- svstate.maxvl[0:7] = 2 # MAXVL
- print ("SVSTATE", bin(svstate.spr.asint()))
- # copy before running
- expected_regs = deepcopy(initial_regs)
- expected_regs[1] = 0x5555
-
- with Program(lst, bigendian=False) as program:
- sim = self.run_tst_program(program, initial_regs, svstate)
- self._check_regs(sim, expected_regs)
-
- def tst_sv_add_3(self):
- # adds:
- # 1 = 5 + 9 => 0x5555 = 0x4321+0x1234
- # 2 = 5 + 10 => 0x5432 = 0x4321+0x1111
- isa = SVP64Asm(['sv.add 1.v, 5, 9.v'
- ])
- lst = list(isa)
- print ("listing", lst)
-
- # initial values in GPR regfile
- initial_regs = [0] * 32
- initial_regs[9] = 0x1234
- initial_regs[10] = 0x1111
- initial_regs[5] = 0x4321
- initial_regs[6] = 0x2223
- # SVSTATE (in this case, VL=2)
- svstate = SVP64State()
- svstate.vl[0:7] = 2 # VL
- svstate.maxvl[0:7] = 2 # MAXVL
- print ("SVSTATE", bin(svstate.spr.asint()))
- # copy before running
- expected_regs = deepcopy(initial_regs)
- expected_regs[1] = 0x5555
- expected_regs[2] = 0x5432
-
- with Program(lst, bigendian=False) as program:
- sim = self.run_tst_program(program, initial_regs, svstate)
- self._check_regs(sim, expected_regs)
-
- def tst_sv_add_vl_0(self):
- # adds:
- # none because VL is zer0
- isa = SVP64Asm(['sv.add 1, 5.v, 9.v'
- ])
- lst = list(isa)
- print ("listing", lst)
-
- # initial values in GPR regfile
- initial_regs = [0] * 32
- initial_regs[9] = 0x1234
- initial_regs[10] = 0x1111
- initial_regs[5] = 0x4321
- initial_regs[6] = 0x2223
- # SVSTATE (in this case, VL=0)
- svstate = SVP64State()
- svstate.vl[0:7] = 0 # VL
- svstate.maxvl[0:7] = 0 # MAXVL
- print ("SVSTATE", bin(svstate.spr.asint()))
- # copy before running
- expected_regs = deepcopy(initial_regs)
-
- with Program(lst, bigendian=False) as program:
- sim = self.run_tst_program(program, initial_regs, svstate)
- self._check_regs(sim, expected_regs)
-
- def tst_sv_add_cr(self):
- # adds when Rc=1: TODO CRs higher up
- # 1 = 5 + 9 => 0 = -1+1 CR0=0b100
- # 2 = 6 + 10 => 0x3334 = 0x2223+0x1111 CR1=0b010
- isa = SVP64Asm(['sv.add. 1.v, 5.v, 9.v'
- ])
- lst = list(isa)
- print ("listing", lst)
-
- # initial values in GPR regfile
- initial_regs = [0] * 32
- initial_regs[9] = 0xffffffffffffffff
- initial_regs[10] = 0x1111
- initial_regs[5] = 0x1
- initial_regs[6] = 0x2223
- # SVSTATE (in this case, VL=2)
- svstate = SVP64State()
- svstate.vl[0:7] = 2 # VL
- svstate.maxvl[0:7] = 2 # MAXVL
- print ("SVSTATE", bin(svstate.spr.asint()))
- # copy before running
- expected_regs = deepcopy(initial_regs)
- expected_regs[1] = 0
- expected_regs[2] = 0x3334
-
- with Program(lst, bigendian=False) as program:
- sim = self.run_tst_program(program, initial_regs, svstate)
- # XXX TODO, these need to move to higher range (offset)
- cr0_idx = SVP64CROffs.CR0
- cr1_idx = SVP64CROffs.CR1
- CR0 = sim.crl[cr0_idx].get_range().value
- CR1 = sim.crl[cr1_idx].get_range().value
- print ("CR0", CR0)
- print ("CR1", CR1)
- self._check_regs(sim, expected_regs)
- self.assertEqual(CR0, SelectableInt(2, 4))
- self.assertEqual(CR1, SelectableInt(4, 4))
-
def test_intpred_vcompress(self):
# reg num 0 1 2 3 4 5 6 7 8 9 10 11
# src r3=0b101 Y N Y
# | |
# dest always Y Y Y
- isa = SVP64Asm(['sv.extsb/sm=r3 5.v, 9.v'])
+ isa = SVP64Asm(['sv.extsb/sm=r3 *5, *9'])
lst = list(isa)
print("listing", lst)
initial_regs[11] = 0x92 # source r3 is 0b101 so this will be used
# SVSTATE (in this case, VL=3)
svstate = SVP64State()
- svstate.vl[0:7] = 3 # VL
- svstate.maxvl[0:7] = 3 # MAXVL
- print("SVSTATE", bin(svstate.spr.asint()))
+ svstate.vl = 3 # VL
+ svstate.maxvl = 3 # MAXVL
+ print("SVSTATE", bin(svstate.asint()))
# copy before running
expected_regs = deepcopy(initial_regs)
expected_regs[5] = 0xffff_ffff_ffff_ff90 # (from r9)
# | |
# dest r3=0b101 Y N Y
- isa = SVP64Asm(['sv.extsb/dm=r3 5.v, 9.v'])
+ isa = SVP64Asm(['sv.extsb/dm=r3 *5, *9'])
lst = list(isa)
print("listing", lst)
initial_regs[11] = 0x92 # the VL loop runs out before we can use it
# SVSTATE (in this case, VL=3)
svstate = SVP64State()
- svstate.vl[0:7] = 3 # VL
- svstate.maxvl[0:7] = 3 # MAXVL
- print("SVSTATE", bin(svstate.spr.asint()))
+ svstate.vl = 3 # VL
+ svstate.maxvl = 3 # MAXVL
+ print("SVSTATE", bin(svstate.asint()))
# copy before running
expected_regs = deepcopy(initial_regs)
expected_regs[5] = 0xffff_ffff_ffff_ff90 # 1st bit of r3 is 1
# |
# dest ~r3=0b010 N Y N
- isa = SVP64Asm(['sv.extsb/sm=r3/dm=~r3 5.v, 9.v'])
+ isa = SVP64Asm(['sv.extsb/sm=r3/dm=~r3 *5, *9'])
lst = list(isa)
print("listing", lst)
initial_regs[11] = 0x92 # VL loop runs out before we can use it
# SVSTATE (in this case, VL=3)
svstate = SVP64State()
- svstate.vl[0:7] = 3 # VL
- svstate.maxvl[0:7] = 3 # MAXVL
- print("SVSTATE", bin(svstate.spr.asint()))
+ svstate.vl = 3 # VL
+ svstate.maxvl = 3 # MAXVL
+ print("SVSTATE", bin(svstate.asint()))
# copy before running
expected_regs = deepcopy(initial_regs)
expected_regs[5] = 0x0 # dest ~r3 is 0b010: skip
# dest ~r3=0b1010 N Y N Y
# dststep=2 ^
- isa = SVP64Asm(['sv.extsb/sm=r3/dm=~r3 5.v, 9.v'])
+ isa = SVP64Asm(['sv.extsb/sm=r3/dm=~r3 *5, *9'])
lst = list(isa)
print("listing", lst)
# SVSTATE (in this case, VL=4)
svstate = SVP64State()
- svstate.vl[0:7] = 4 # VL
- svstate.maxvl[0:7] = 4 # MAXVL
+ svstate.vl = 4 # VL
+ svstate.maxvl = 4 # MAXVL
# set src/dest step on the middle of the loop
- svstate.srcstep[0:7] = 1
- svstate.dststep[0:7] = 2
- print("SVSTATE", bin(svstate.spr.asint()))
+ svstate.srcstep = 1
+ svstate.dststep = 2
+ print("SVSTATE", bin(svstate.asint()))
# copy before running
expected_regs = deepcopy(initial_regs)
expected_regs[5] = 0x0 # skip
# |
# dest r3=1: 1<<r3=0b010 N Y N
- isa = SVP64Asm(['sv.extsb/dm=1<<r3/sm=r30 5.v, 9.v'])
+ isa = SVP64Asm(['sv.extsb/dm=1<<r3/sm=r30 *5, *9'])
lst = list(isa)
print("listing", lst)
initial_regs[11] = 0x92 # 3rd bit of r30 is 1
# SVSTATE (in this case, VL=3)
svstate = SVP64State()
- svstate.vl[0:7] = 3 # VL
- svstate.maxvl[0:7] = 3 # MAXVL
- print("SVSTATE", bin(svstate.spr.asint()))
+ svstate.vl = 3 # VL
+ svstate.maxvl = 3 # MAXVL
+ print("SVSTATE", bin(svstate.asint()))
# copy before running
expected_regs = deepcopy(initial_regs)
expected_regs[5] = 0x0 # skip
# |
# dest r30=0b010 N Y N
- isa = SVP64Asm(['sv.extsb/sm=1<<r3/dm=r30 5.v, 9.v'])
+ isa = SVP64Asm(['sv.extsb/sm=1<<r3/dm=r30 *5, *9'])
lst = list(isa)
print("listing", lst)
initial_regs[11] = 0x92 # r3 is 2, so this will be used
# SVSTATE (in this case, VL=3)
svstate = SVP64State()
- svstate.vl[0:7] = 3 # VL
- svstate.maxvl[0:7] = 3 # MAXVL
- print("SVSTATE", bin(svstate.spr.asint()))
+ svstate.vl = 3 # VL
+ svstate.maxvl = 3 # MAXVL
+ print("SVSTATE", bin(svstate.asint()))
# copy before running
expected_regs = deepcopy(initial_regs)
expected_regs[5] = 0x0 # skip
sim = self.run_tst_program(program, initial_regs, svstate)
self._check_regs(sim, expected_regs)
+ # checks reentrant CR predication
+ def test_crpred_reentrant(self):
+ # reg num 0 1 2 3 4 5 6 7 8 9 10 11 12
+ # srcstep=1 v
+ # src cr4.eq=1 Y N Y N
+ # cr6.eq=1 : |
+ # + - - + |
+ # : +-------+
+ # dest cr5.lt=1 : |
+ # cr7.lt=1 N Y N Y
+ # dststep=2 ^
+
+ isa = SVP64Asm(['sv.extsb/sm=eq/dm=lt *5, *9'])
+ lst = list(isa)
+ print("listing", lst)
+
+ # initial values in GPR regfile
+ initial_regs = [0] * 32
+ initial_regs[9] = 0x90 # srcstep starts at 2, so this gets skipped
+ initial_regs[10] = 0x91 # skip
+ initial_regs[11] = 0x92 # this will be used
+ initial_regs[12] = 0x93 # skip
+
+ cr = CRFields()
+ # set up CR predicate
+ # CR4.eq=1 and CR6.eq=1
+ cr.crl[4][CRFields.EQ] = 1
+ cr.crl[6][CRFields.EQ] = 1
+ # CR5.lt=1 and CR7.lt=1
+ cr.crl[5][CRFields.LT] = 1
+ cr.crl[7][CRFields.LT] = 1
+ # SVSTATE (in this case, VL=4)
+ svstate = SVP64State()
+ svstate.vl = 4 # VL
+ svstate.maxvl = 4 # MAXVL
+ # set src/dest step on the middle of the loop
+ svstate.srcstep = 1
+ svstate.dststep = 2
+ print("SVSTATE", bin(svstate.asint()))
+ # copy before running
+ expected_regs = deepcopy(initial_regs)
+ expected_regs[5] = 0x0 # skip
+ expected_regs[6] = 0x0 # dststep starts at 3, so this gets skipped
+ expected_regs[7] = 0x0 # skip
+ expected_regs[8] = 0xffff_ffff_ffff_ff92 # this will be used
+
+ with Program(lst, bigendian=False) as program:
+ sim = self.run_tst_program(program, initial_regs, svstate,
+ initial_cr=cr.cr.asint())
+ self._check_regs(sim, expected_regs)
+
def run_tst_program(self, prog, initial_regs=None,
svstate=None,
initial_cr=0):