# SVSTATE (in this case, VL=2)
svstate = SVP64State()
- svstate.vl[0:7] = 2 # VL
- svstate.maxvl[0:7] = 2 # MAXVL
- print ("SVSTATE", bin(svstate.spr.asint()))
+ svstate.vl = 2 # VL
+ svstate.maxvl = 2 # MAXVL
+ print ("SVSTATE", bin(svstate.asint()))
with Program(lst, bigendian=False) as program:
sim = self.run_tst_program(program, svstate=svstate)
initial_regs[10] = 0x90 # this gets skipped
# SVSTATE (in this case, VL=2)
svstate = SVP64State()
- svstate.vl[0:7] = 2 # VL
- svstate.maxvl[0:7] = 2 # MAXVL
- print ("SVSTATE", bin(svstate.spr.asint()))
+ svstate.vl = 2 # VL
+ svstate.maxvl = 2 # MAXVL
+ print ("SVSTATE", bin(svstate.asint()))
# copy before running
expected_regs = deepcopy(initial_regs)
expected_regs[5] = 0x0 # dest r3 is 0b10: skip
initial_regs[10] = 0x90 # this gets read but the output gets zero'd
# SVSTATE (in this case, VL=2)
svstate = SVP64State()
- svstate.vl[0:7] = 2 # VL
- svstate.maxvl[0:7] = 2 # MAXVL
- print ("SVSTATE", bin(svstate.spr.asint()))
+ svstate.vl = 2 # VL
+ svstate.maxvl = 2 # MAXVL
+ print ("SVSTATE", bin(svstate.asint()))
# copy before running
expected_regs = deepcopy(initial_regs)
expected_regs[5] = 0xffff_ffff_ffff_ff91 # dest r3 is 0b01: store
# adds, integer predicated mask r3=0b10
# 1 = 5 + 9 => not to be touched (skipped)
# 2 = 6 + 10 => 0x3334 = 0x2223+0x1111
+ # reg num 0 1 2 3 4 5 6 7 8 9 10 11
+ # src r3=0b10 N Y N Y
+ # | | | |
+ # +-------+ | add + |
+ # | +-------+ add --+
+ # | |
+ # dest r3=0b10 N Y
isa = SVP64Asm(['sv.add/m=r3 1.v, 5.v, 9.v'
])
lst = list(isa)
initial_regs[6] = 0x2223
# SVSTATE (in this case, VL=2)
svstate = SVP64State()
- svstate.vl[0:7] = 2 # VL
- svstate.maxvl[0:7] = 2 # MAXVL
- print ("SVSTATE", bin(svstate.spr.asint()))
+ svstate.vl = 2 # VL
+ svstate.maxvl = 2 # MAXVL
+ print ("SVSTATE", bin(svstate.asint()))
# copy before running
expected_regs = deepcopy(initial_regs)
expected_regs[1] = 0xbeef
initial_regs[6] = 0x2223
# SVSTATE (in this case, VL=2)
svstate = SVP64State()
- svstate.vl[0:7] = 2 # VL
- svstate.maxvl[0:7] = 2 # MAXVL
- print ("SVSTATE", bin(svstate.spr.asint()))
+ svstate.vl = 2 # VL
+ svstate.maxvl = 2 # MAXVL
+ print ("SVSTATE", bin(svstate.asint()))
# copy before running
expected_regs = deepcopy(initial_regs)
expected_regs[1] = 0xbeef
initial_regs[11] = 0x92 # source r3 is 0b101 so this will be used
# SVSTATE (in this case, VL=3)
svstate = SVP64State()
- svstate.vl[0:7] = 3 # VL
- svstate.maxvl[0:7] = 3 # MAXVL
- print("SVSTATE", bin(svstate.spr.asint()))
+ svstate.vl = 3 # VL
+ svstate.maxvl = 3 # MAXVL
+ print("SVSTATE", bin(svstate.asint()))
# copy before running
expected_regs = deepcopy(initial_regs)
expected_regs[5] = 0xffff_ffff_ffff_ff90 # (from r9)
initial_regs[11] = 0x92 # the VL loop runs out before we can use it
# SVSTATE (in this case, VL=3)
svstate = SVP64State()
- svstate.vl[0:7] = 3 # VL
- svstate.maxvl[0:7] = 3 # MAXVL
- print("SVSTATE", bin(svstate.spr.asint()))
+ svstate.vl = 3 # VL
+ svstate.maxvl = 3 # MAXVL
+ print("SVSTATE", bin(svstate.asint()))
# copy before running
expected_regs = deepcopy(initial_regs)
expected_regs[5] = 0xffff_ffff_ffff_ff90 # 1st bit of r3 is 1
initial_regs[11] = 0x92 # VL loop runs out before we can use it
# SVSTATE (in this case, VL=3)
svstate = SVP64State()
- svstate.vl[0:7] = 3 # VL
- svstate.maxvl[0:7] = 3 # MAXVL
- print("SVSTATE", bin(svstate.spr.asint()))
+ svstate.vl = 3 # VL
+ svstate.maxvl = 3 # MAXVL
+ print("SVSTATE", bin(svstate.asint()))
# copy before running
expected_regs = deepcopy(initial_regs)
expected_regs[5] = 0x0 # dest ~r3 is 0b010: skip
# SVSTATE (in this case, VL=4)
svstate = SVP64State()
- svstate.vl[0:7] = 4 # VL
- svstate.maxvl[0:7] = 4 # MAXVL
+ svstate.vl = 4 # VL
+ svstate.maxvl = 4 # MAXVL
# set src/dest step on the middle of the loop
- svstate.srcstep[0:7] = 1
- svstate.dststep[0:7] = 2
- print("SVSTATE", bin(svstate.spr.asint()))
+ svstate.srcstep = 1
+ svstate.dststep = 2
+ print("SVSTATE", bin(svstate.asint()))
# copy before running
expected_regs = deepcopy(initial_regs)
expected_regs[5] = 0x0 # skip
initial_regs[11] = 0x92 # 3rd bit of r30 is 1
# SVSTATE (in this case, VL=3)
svstate = SVP64State()
- svstate.vl[0:7] = 3 # VL
- svstate.maxvl[0:7] = 3 # MAXVL
- print("SVSTATE", bin(svstate.spr.asint()))
+ svstate.vl = 3 # VL
+ svstate.maxvl = 3 # MAXVL
+ print("SVSTATE", bin(svstate.asint()))
# copy before running
expected_regs = deepcopy(initial_regs)
expected_regs[5] = 0x0 # skip
initial_regs[11] = 0x92 # r3 is 2, so this will be used
# SVSTATE (in this case, VL=3)
svstate = SVP64State()
- svstate.vl[0:7] = 3 # VL
- svstate.maxvl[0:7] = 3 # MAXVL
- print("SVSTATE", bin(svstate.spr.asint()))
+ svstate.vl = 3 # VL
+ svstate.maxvl = 3 # MAXVL
+ print("SVSTATE", bin(svstate.asint()))
# copy before running
expected_regs = deepcopy(initial_regs)
expected_regs[5] = 0x0 # skip
cr.crl[7][CRFields.LT] = 1
# SVSTATE (in this case, VL=4)
svstate = SVP64State()
- svstate.vl[0:7] = 4 # VL
- svstate.maxvl[0:7] = 4 # MAXVL
+ svstate.vl = 4 # VL
+ svstate.maxvl = 4 # MAXVL
# set src/dest step on the middle of the loop
- svstate.srcstep[0:7] = 1
- svstate.dststep[0:7] = 2
- print("SVSTATE", bin(svstate.spr.asint()))
+ svstate.srcstep = 1
+ svstate.dststep = 2
+ print("SVSTATE", bin(svstate.asint()))
# copy before running
expected_regs = deepcopy(initial_regs)
expected_regs[5] = 0x0 # skip