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[openpower-isa.git] / src / openpower / decoder / isa / test_caller_svp64_predication.py
diff --git a/src/openpower/decoder/isa/test_caller_svp64_predication.py b/src/openpower/decoder/isa/test_caller_svp64_predication.py
index df55ca99887d5371fa29c7e0ac5d43928d874fce..c34094eee29718c9134afedd8cc2da5c53938f22 100644 (file)
--- a/src/openpower/decoder/isa/test_caller_svp64_predication.py
+++ b/src/openpower/decoder/isa/test_caller_svp64_predication.py
@@ -32,9 +32,9 @@ class DecoderTestCase(FHDLTestCase):
 
         # SVSTATE (in this case, VL=2)
         svstate = SVP64State()
-        svstate.vl[0:7] = 2 # VL
-        svstate.maxvl[0:7] = 2 # MAXVL
-        print ("SVSTATE", bin(svstate.spr.asint()))
+        svstate.vl = 2 # VL
+        svstate.maxvl = 2 # MAXVL
+        print ("SVSTATE", bin(svstate.asint()))
 
         with Program(lst, bigendian=False) as program:
             sim = self.run_tst_program(program, svstate=svstate)
@@ -76,9 +76,9 @@ class DecoderTestCase(FHDLTestCase):
         initial_regs[10] = 0x90  # this gets skipped
         # SVSTATE (in this case, VL=2)
         svstate = SVP64State()
-        svstate.vl[0:7] = 2 # VL
-        svstate.maxvl[0:7] = 2 # MAXVL
-        print ("SVSTATE", bin(svstate.spr.asint()))
+        svstate.vl = 2 # VL
+        svstate.maxvl = 2 # MAXVL
+        print ("SVSTATE", bin(svstate.asint()))
         # copy before running
         expected_regs = deepcopy(initial_regs)
         expected_regs[5] = 0x0                   # dest r3 is 0b10: skip
@@ -104,9 +104,9 @@ class DecoderTestCase(FHDLTestCase):
         initial_regs[10] = 0x90  # this gets read but the output gets zero'd
         # SVSTATE (in this case, VL=2)
         svstate = SVP64State()
-        svstate.vl[0:7] = 2 # VL
-        svstate.maxvl[0:7] = 2 # MAXVL
-        print ("SVSTATE", bin(svstate.spr.asint()))
+        svstate.vl = 2 # VL
+        svstate.maxvl = 2 # MAXVL
+        print ("SVSTATE", bin(svstate.asint()))
         # copy before running
         expected_regs = deepcopy(initial_regs)
         expected_regs[5] = 0xffff_ffff_ffff_ff91 # dest r3 is 0b01: store
@@ -120,6 +120,13 @@ class DecoderTestCase(FHDLTestCase):
         # adds, integer predicated mask r3=0b10
         #       1 = 5 + 9   => not to be touched (skipped)
         #       2 = 6 + 10  => 0x3334 = 0x2223+0x1111
+        #   reg num        0 1 2 3 4 5 6 7 8 9 10 11
+        #   src r3=0b10              N Y     N Y
+        #                            | |     | |
+        #                    +-------+ | add + |
+        #                    | +-------+ add --+
+        #                    | |
+        #   dest r3=0b10     N Y
         isa = SVP64Asm(['sv.add/m=r3 1.v, 5.v, 9.v'
                        ])
         lst = list(isa)
@@ -135,9 +142,9 @@ class DecoderTestCase(FHDLTestCase):
         initial_regs[6] = 0x2223
         # SVSTATE (in this case, VL=2)
         svstate = SVP64State()
-        svstate.vl[0:7] = 2 # VL
-        svstate.maxvl[0:7] = 2 # MAXVL
-        print ("SVSTATE", bin(svstate.spr.asint()))
+        svstate.vl = 2 # VL
+        svstate.maxvl = 2 # MAXVL
+        print ("SVSTATE", bin(svstate.asint()))
         # copy before running
         expected_regs = deepcopy(initial_regs)
         expected_regs[1] = 0xbeef
@@ -165,9 +172,9 @@ class DecoderTestCase(FHDLTestCase):
         initial_regs[6] = 0x2223
         # SVSTATE (in this case, VL=2)
         svstate = SVP64State()
-        svstate.vl[0:7] = 2 # VL
-        svstate.maxvl[0:7] = 2 # MAXVL
-        print ("SVSTATE", bin(svstate.spr.asint()))
+        svstate.vl = 2 # VL
+        svstate.maxvl = 2 # MAXVL
+        print ("SVSTATE", bin(svstate.asint()))
         # copy before running
         expected_regs = deepcopy(initial_regs)
         expected_regs[1] = 0xbeef
@@ -181,127 +188,6 @@ class DecoderTestCase(FHDLTestCase):
                                        initial_cr=cr)
             self._check_regs(sim, expected_regs)
 
-    def tst_sv_add_2(self):
-        # adds:
-        #       1 = 5 + 9   => 0x5555 = 0x4321+0x1234
-        #       r1 is scalar so ENDS EARLY
-        isa = SVP64Asm(['sv.add 1, 5.v, 9.v'
-                       ])
-        lst = list(isa)
-        print ("listing", lst)
-
-        # initial values in GPR regfile
-        initial_regs = [0] * 32
-        initial_regs[9] = 0x1234
-        initial_regs[10] = 0x1111
-        initial_regs[5] = 0x4321
-        initial_regs[6] = 0x2223
-        # SVSTATE (in this case, VL=2)
-        svstate = SVP64State()
-        svstate.vl[0:7] = 2 # VL
-        svstate.maxvl[0:7] = 2 # MAXVL
-        print ("SVSTATE", bin(svstate.spr.asint()))
-        # copy before running
-        expected_regs = deepcopy(initial_regs)
-        expected_regs[1] = 0x5555
-
-        with Program(lst, bigendian=False) as program:
-            sim = self.run_tst_program(program, initial_regs, svstate)
-            self._check_regs(sim, expected_regs)
-
-    def tst_sv_add_3(self):
-        # adds:
-        #       1 = 5 + 9   => 0x5555 = 0x4321+0x1234
-        #       2 = 5 + 10  => 0x5432 = 0x4321+0x1111
-        isa = SVP64Asm(['sv.add 1.v, 5, 9.v'
-                       ])
-        lst = list(isa)
-        print ("listing", lst)
-
-        # initial values in GPR regfile
-        initial_regs = [0] * 32
-        initial_regs[9] = 0x1234
-        initial_regs[10] = 0x1111
-        initial_regs[5] = 0x4321
-        initial_regs[6] = 0x2223
-        # SVSTATE (in this case, VL=2)
-        svstate = SVP64State()
-        svstate.vl[0:7] = 2 # VL
-        svstate.maxvl[0:7] = 2 # MAXVL
-        print ("SVSTATE", bin(svstate.spr.asint()))
-        # copy before running
-        expected_regs = deepcopy(initial_regs)
-        expected_regs[1] = 0x5555
-        expected_regs[2] = 0x5432
-
-        with Program(lst, bigendian=False) as program:
-            sim = self.run_tst_program(program, initial_regs, svstate)
-            self._check_regs(sim, expected_regs)
-
-    def tst_sv_add_vl_0(self):
-        # adds:
-        #       none because VL is zer0
-        isa = SVP64Asm(['sv.add 1, 5.v, 9.v'
-                       ])
-        lst = list(isa)
-        print ("listing", lst)
-
-        # initial values in GPR regfile
-        initial_regs = [0] * 32
-        initial_regs[9] = 0x1234
-        initial_regs[10] = 0x1111
-        initial_regs[5] = 0x4321
-        initial_regs[6] = 0x2223
-        # SVSTATE (in this case, VL=0)
-        svstate = SVP64State()
-        svstate.vl[0:7] = 0 # VL
-        svstate.maxvl[0:7] = 0 # MAXVL
-        print ("SVSTATE", bin(svstate.spr.asint()))
-        # copy before running
-        expected_regs = deepcopy(initial_regs)
-
-        with Program(lst, bigendian=False) as program:
-            sim = self.run_tst_program(program, initial_regs, svstate)
-            self._check_regs(sim, expected_regs)
-
-    def tst_sv_add_cr(self):
-        # adds when Rc=1:                               TODO CRs higher up
-        #       1 = 5 + 9   => 0 = -1+1                 CR0=0b100
-        #       2 = 6 + 10  => 0x3334 = 0x2223+0x1111   CR1=0b010
-        isa = SVP64Asm(['sv.add. 1.v, 5.v, 9.v'
-                       ])
-        lst = list(isa)
-        print ("listing", lst)
-
-        # initial values in GPR regfile
-        initial_regs = [0] * 32
-        initial_regs[9] = 0xffffffffffffffff
-        initial_regs[10] = 0x1111
-        initial_regs[5] = 0x1
-        initial_regs[6] = 0x2223
-        # SVSTATE (in this case, VL=2)
-        svstate = SVP64State()
-        svstate.vl[0:7] = 2 # VL
-        svstate.maxvl[0:7] = 2 # MAXVL
-        print ("SVSTATE", bin(svstate.spr.asint()))
-        # copy before running
-        expected_regs = deepcopy(initial_regs)
-        expected_regs[1] = 0
-        expected_regs[2] = 0x3334
-
-        with Program(lst, bigendian=False) as program:
-            sim = self.run_tst_program(program, initial_regs, svstate)
-            # XXX TODO, these need to move to higher range (offset)
-            cr0_idx = SVP64CROffs.CR0
-            cr1_idx = SVP64CROffs.CR1
-            CR0 = sim.crl[cr0_idx].get_range().value
-            CR1 = sim.crl[cr1_idx].get_range().value
-            print ("CR0", CR0)
-            print ("CR1", CR1)
-            self._check_regs(sim, expected_regs)
-            self.assertEqual(CR0, SelectableInt(2, 4))
-            self.assertEqual(CR1, SelectableInt(4, 4))
-
     def test_intpred_vcompress(self):
         #   reg num        0 1 2 3 4 5 6 7 8 9 10 11
         #   src r3=0b101                     Y  N  Y
@@ -323,9 +209,9 @@ class DecoderTestCase(FHDLTestCase):
         initial_regs[11] = 0x92  # source r3 is 0b101 so this will be used
         # SVSTATE (in this case, VL=3)
         svstate = SVP64State()
-        svstate.vl[0:7] = 3  # VL
-        svstate.maxvl[0:7] = 3  # MAXVL
-        print("SVSTATE", bin(svstate.spr.asint()))
+        svstate.vl = 3  # VL
+        svstate.maxvl = 3  # MAXVL
+        print("SVSTATE", bin(svstate.asint()))
         # copy before running
         expected_regs = deepcopy(initial_regs)
         expected_regs[5] = 0xffff_ffff_ffff_ff90  # (from r9)
@@ -357,9 +243,9 @@ class DecoderTestCase(FHDLTestCase):
         initial_regs[11] = 0x92  # the VL loop runs out before we can use it
         # SVSTATE (in this case, VL=3)
         svstate = SVP64State()
-        svstate.vl[0:7] = 3  # VL
-        svstate.maxvl[0:7] = 3  # MAXVL
-        print("SVSTATE", bin(svstate.spr.asint()))
+        svstate.vl = 3  # VL
+        svstate.maxvl = 3  # MAXVL
+        print("SVSTATE", bin(svstate.asint()))
         # copy before running
         expected_regs = deepcopy(initial_regs)
         expected_regs[5] = 0xffff_ffff_ffff_ff90  # 1st bit of r3 is 1
@@ -390,9 +276,9 @@ class DecoderTestCase(FHDLTestCase):
         initial_regs[11] = 0x92  # VL loop runs out before we can use it
         # SVSTATE (in this case, VL=3)
         svstate = SVP64State()
-        svstate.vl[0:7] = 3  # VL
-        svstate.maxvl[0:7] = 3  # MAXVL
-        print("SVSTATE", bin(svstate.spr.asint()))
+        svstate.vl = 3  # VL
+        svstate.maxvl = 3  # MAXVL
+        print("SVSTATE", bin(svstate.asint()))
         # copy before running
         expected_regs = deepcopy(initial_regs)
         expected_regs[5] = 0x0  # dest ~r3 is 0b010: skip
@@ -432,12 +318,12 @@ class DecoderTestCase(FHDLTestCase):
 
         # SVSTATE (in this case, VL=4)
         svstate = SVP64State()
-        svstate.vl[0:7] = 4  # VL
-        svstate.maxvl[0:7] = 4  # MAXVL
+        svstate.vl = 4  # VL
+        svstate.maxvl = 4  # MAXVL
         # set src/dest step on the middle of the loop
-        svstate.srcstep[0:7] = 1
-        svstate.dststep[0:7] = 2
-        print("SVSTATE", bin(svstate.spr.asint()))
+        svstate.srcstep = 1
+        svstate.dststep = 2
+        print("SVSTATE", bin(svstate.asint()))
         # copy before running
         expected_regs = deepcopy(initial_regs)
         expected_regs[5] = 0x0  # skip
@@ -470,9 +356,9 @@ class DecoderTestCase(FHDLTestCase):
         initial_regs[11] = 0x92  # 3rd bit of r30 is 1
         # SVSTATE (in this case, VL=3)
         svstate = SVP64State()
-        svstate.vl[0:7] = 3  # VL
-        svstate.maxvl[0:7] = 3  # MAXVL
-        print("SVSTATE", bin(svstate.spr.asint()))
+        svstate.vl = 3  # VL
+        svstate.maxvl = 3  # MAXVL
+        print("SVSTATE", bin(svstate.asint()))
         # copy before running
         expected_regs = deepcopy(initial_regs)
         expected_regs[5] = 0x0  # skip
@@ -504,9 +390,9 @@ class DecoderTestCase(FHDLTestCase):
         initial_regs[11] = 0x92  # r3 is 2, so this will be used
         # SVSTATE (in this case, VL=3)
         svstate = SVP64State()
-        svstate.vl[0:7] = 3  # VL
-        svstate.maxvl[0:7] = 3  # MAXVL
-        print("SVSTATE", bin(svstate.spr.asint()))
+        svstate.vl = 3  # VL
+        svstate.maxvl = 3  # MAXVL
+        print("SVSTATE", bin(svstate.asint()))
         # copy before running
         expected_regs = deepcopy(initial_regs)
         expected_regs[5] = 0x0  # skip
@@ -550,12 +436,12 @@ class DecoderTestCase(FHDLTestCase):
         cr.crl[7][CRFields.LT] = 1
         # SVSTATE (in this case, VL=4)
         svstate = SVP64State()
-        svstate.vl[0:7] = 4  # VL
-        svstate.maxvl[0:7] = 4  # MAXVL
+        svstate.vl = 4  # VL
+        svstate.maxvl = 4  # MAXVL
         # set src/dest step on the middle of the loop
-        svstate.srcstep[0:7] = 1
-        svstate.dststep[0:7] = 2
-        print("SVSTATE", bin(svstate.spr.asint()))
+        svstate.srcstep = 1
+        svstate.dststep = 2
+        print("SVSTATE", bin(svstate.asint()))
         # copy before running
         expected_regs = deepcopy(initial_regs)
         expected_regs[5] = 0x0  # skip