from nmigen import Module, Signal
-from nmigen.back.pysim import Simulator, Delay, Settle
+from nmigen.sim import Simulator, Delay, Settle
from nmutil.formaltest import FHDLTestCase
import unittest
from openpower.decoder.isa.caller import ISACaller
from copy import deepcopy
from openpower.sv.trans.svp64 import SVP64Asm
from openpower.decoder.helpers import fp64toselectable
-from openpower.decoder.isafunctions.double2single import DOUBLE2SINGLE
+from openpower.decoder.isafunctions.double2single import ISACallerFnHelper
+
+# really bad hack. need to access the DOUBLE2SINGLE function auto-generated
+# from pseudo-code.
+fph = ISACallerFnHelper(XLEN=64)
+
import math
t = math.sin(a)
u = math.cos(a)
a1 = fp64toselectable(a) # convert to Power single
- t = DOUBLE2SINGLE(fp64toselectable(t)) # convert to Power single
- u = DOUBLE2SINGLE(fp64toselectable(u)) # convert to Power single
+ t = fph.DOUBLE2SINGLE(fp64toselectable(t)) # to Power single
+ u = fph.DOUBLE2SINGLE(fp64toselectable(u)) # to Power single
with self.subTest():
sim = self.run_tst_program(program, initial_fprs=fprs)
""">>> lst = [
"fcoss 3, 2",
]
+
+ this is a base / proving-ground for the more complex SVP64
+ variant in test_caller_svp64_dct.py:
+ test_sv_remap_dct_cos_precompute_8
"""
- lst = SVP64Asm(["stw 1, 0(0)",
+ lst = SVP64Asm(["std 1, 0(0)",
"lfd 0, 0(0)",
"fcfids 0, 0",
"fadds 0, 0, 3", # plus 0.5
for i in range(7, 8):
a = math.pi * ((i+0.5) / 4.0)
gprs[1] = i
- a1 = DOUBLE2SINGLE(fp64toselectable(a)) # to Power single
+ a1 = fph.DOUBLE2SINGLE(fp64toselectable(a)) # to Power single
a = float(a1)
u = math.cos(a)
- u = DOUBLE2SINGLE(fp64toselectable(u)) # convert to Power single
+ u = fph.DOUBLE2SINGLE(fp64toselectable(u)) # to Power single
with self.subTest():
sim = self.run_tst_program(program, gprs, initial_fprs=fprs)