bug #672: invert testing in sv.minmax and add Rc=1

[openpower-isa.git] / src / openpower / decoder / power_decoder.py

diff --git a/src/openpower/decoder/power_decoder.py b/src/openpower/decoder/power_decoder.py
index 9da38df7f1c1643ba1e42640cecd6d24594d8785..4bf1e351afa865cd8ae2121eb666e4ee5794c866 100644 (file)
--- a/src/openpower/decoder/power_decoder.py
+++ b/src/openpower/decoder/power_decoder.py
@@ -93,8 +93,9 @@ from nmigen import Module, Elaboratable, Signal, Cat, Mux, Const
 from nmigen.cli import rtlil, verilog
 from openpower.decoder.power_enums import (Function, Form, MicrOp,
                                            In1Sel, In2Sel, In3Sel, OutSel,
-                                           SVEXTRA, SVEtype, SVPtype, # Simple-V
-                                           RC, LdstLen, LDSTMode, CryIn,
+                                           SVEXTRA, SVMode, # Simple-V
+                                           SVEType, SVPType, # Simple-V
+                                           RCOE, LdstLen, LDSTMode, CryIn,
                                            single_bit_flags, CRInSel,
                                            CROutSel, get_signal_name,
                                            default_values, insns, asmidx,
@@ -123,8 +124,9 @@ power_op_types = {'function_unit': Function,
                   'internal_op': MicrOp,
                   'form': Form,
                   'asmcode': asmlen,
-                  'SV_Etype': SVEtype,
-                  'SV_Ptype': SVPtype,
+                  'SV_Etype': SVEType,
+                  'SV_Ptype': SVPType,
+                  'SV_mode': SVMode,
                   'in1_sel': In1Sel,
                   'in2_sel': In2Sel,
                   'in3_sel': In3Sel,
@@ -140,7 +142,7 @@ power_op_types = {'function_unit': Function,
                   'sv_cr_out': SVEXTRA,
                   'ldst_len': LdstLen,
                   'upd': LDSTMode,
-                  'rc_sel': RC,
+                  'rc_sel': RCOE,
                   'cry_in': CryIn
                   }
 
@@ -160,6 +162,7 @@ power_op_csvmap = {'function_unit': 'unit',
                    'sv_cr_out': 'sv_cr_out',
                    'SV_Etype': 'SV_Etype',
                    'SV_Ptype': 'SV_Ptype',
+                   'SV_mode': 'SV_mode',
                    'cr_in': 'CR in',
                    'cr_out': 'CR out',
                    'ldst_len': 'ldst len',
@@ -208,8 +211,8 @@ class PowerOp:
             setattr(self, field, Signal(reset_less=True, name=fname))
         self._fields = fields
         # comment out, bit too high debug level
-        #print("PowerOp debug", name, debug_report)
-        #print("        fields", fields)
+        #log("PowerOp debug", name, debug_report)
+        #log("        fields", fields)
 
     @staticmethod
     def like(other):
@@ -248,7 +251,7 @@ class PowerOp:
             if field not in power_op_csvmap:
                 continue
             csvname = power_op_csvmap[field]
-            # log(field, ptype, csvname, row)
+            log("_eq", field, ptype, csvname, row)
             val = row[csvname]
             if csvname == 'upd' and isinstance(val, int):  # LDSTMode different
                 val = ptype(val)
@@ -386,7 +389,7 @@ class PowerDecoder(Elaboratable):
     def divide_opcodes(self, d):
         divided = {}
         mask = self.suffix_mask(d)
-        #print("mask", hex(mask))
+        #log("mask", hex(mask))
         for row in d.opcodes:
             opcode = row['opcode']
             if d.opint and '-' not in opcode:
@@ -489,11 +492,12 @@ class PowerDecoder(Elaboratable):
                 decs.append(cases)
             if case_does_something:
                 eqs += eq
-                #print("submodule eqs", self.pname, eq)
+                #log("submodule eqs", self.pname, eq)
 
-        #print("submodules", self.pname, submodules)
+        #log("submodules", self.pname, submodules)
 
-        gc.collect()
+        # GC collection is really slow and shouldn't be needed
+        # gc.collect()
         return self.actually_does_something
 
     def handle_subdecoders(self, switch_case, submodules, d):
@@ -502,7 +506,7 @@ class PowerDecoder(Elaboratable):
             if not isinstance(dlist, list):  # XXX HACK: take first pattern
                 dlist = [dlist]
             for dec in dlist:
-                #print("subdec", dec.pattern, self.pname)
+                #log("subdec", dec.pattern, self.pname)
                 mname = get_pname("dec%d" % dec.pattern, self.pname)
                 if mname in submodules:
                     # sigh, HACK...
@@ -513,9 +517,9 @@ class PowerDecoder(Elaboratable):
                                           col_subset=self.col_subset,
                                           row_subset=self.row_subsetfn,
                                           conditions=self.conditions)
-                log("subdecoder", mname, subdecoder)
+                #log("subdecoder", mname, subdecoder)
                 if not subdecoder.tree_analyse():  # doesn't do anything
-                    log("analysed, DELETING", mname)
+                    #log("analysed, DELETING", mname)
                     del subdecoder
                     continue                      # skip
                 submodules[mname] = subdecoder
@@ -526,7 +530,7 @@ class PowerDecoder(Elaboratable):
         return eqs
 
     def elaborate(self, platform):
-        #print("decoder elaborate", self.pname, self.submodules)
+        #log("decoder elaborate", self.pname, self.submodules)
         m = Module()
         comb = m.d.comb
 
@@ -657,7 +661,7 @@ def create_pdecode_svp64_ldst(name=None, col_subset=None, row_subset=None,
 
     subsetting of the PowerOp decoding is possible by setting col_subset
     """
-    log("create_pdecode_svp64_ldst", name, col_subset, row_subset, include_fp)
+    #log("create_pdecode_svp64_ldst", name, col_subset, row_subset, include_fp)
 
     # some alteration to the CSV files is required for SV so we use
     # a class to do it
@@ -707,7 +711,7 @@ def create_pdecode(name=None, col_subset=None, row_subset=None,
 
     NOTE (sigh) the bitsel patterns are in LSB0 order, they should be MSB0
     """
-    log("create_pdecode", name, col_subset, row_subset, include_fp)
+    #log("create_pdecode", name, col_subset, row_subset, include_fp)
 
     # some alteration to the CSV files is required for SV so we use
     # a class to do it
@@ -717,7 +721,7 @@ def create_pdecode(name=None, col_subset=None, row_subset=None,
     # minor 19 has extra patterns
     m19 = []
     m19.append(Subdecoder(pattern=19, opcodes=get_csv("minor_19.csv"),
-                          opint=True, bitsel=(1, 11), suffix=None,
+                          opint=False, bitsel=(1, 11), suffix=None,
                           subdecoders=[]))
     # XXX problem with sub-decoders (can only handle one),
     # sort this another time
@@ -740,6 +744,8 @@ def create_pdecode(name=None, col_subset=None, row_subset=None,
                    opint=False, bitsel=(0, 11), suffix=None, subdecoders=[]),
         Subdecoder(pattern=5, opcodes=get_csv("minor_5.csv"),
                    opint=True, bitsel=(0, 11), suffix=None, subdecoders=[]),
+        Subdecoder(pattern=4, opcodes=get_csv("minor_4.csv"),
+                   opint=True, bitsel=(0, 6), suffix=None, subdecoders=[]),
     ]
 
     # FP 63L/H decoders. TODO: move mffsfamily to separate subdecoder
@@ -799,7 +805,7 @@ if __name__ == '__main__':
         # row subset
 
         def rowsubsetfn(opcode, row):
-            log("row_subset", opcode, row)
+            #log("row_subset", opcode, row)
             return row['unit'] in ['LDST', 'FPU']
 
         conditions = {
@@ -831,7 +837,7 @@ if __name__ == '__main__':
         from nmigen.hdl.ir import Fragment
         elaborated = Fragment.get(pdecode, platform=None)
         elaborated_repr = fragment_repr(elaborated)
-        print(elaborated_repr)
+        #log(elaborated_repr)
 
         exit(0)