+# SPDX-License-Identifier: LGPL-3-or-later
"""Cascading Power ISA Decoder
License: LGPLv3+
from nmigen.cli import rtlil, verilog
from openpower.decoder.power_enums import (Function, Form, MicrOp,
In1Sel, In2Sel, In3Sel, OutSel,
- SVEXTRA, SVEtype, SVPtype, # Simple-V
- RC, LdstLen, LDSTMode, CryIn,
+ SVEXTRA, SVEtype, SVPtype, # Simple-V
+ RCOE, LdstLen, LDSTMode, CryIn,
single_bit_flags, CRInSel,
CROutSel, get_signal_name,
default_values, insns, asmidx,
"opcodes", # a dictionary of minor patterns to find
"opint", # true => the pattern must not be in "10----11" format
# the bits (as a range) against which "pattern" matches
- "bitsel",
+ "bitsel", # should be in MSB0 order but isn't! it's LSB0. um.
"suffix", # shift the opcode down before decoding
"subdecoders" # list of further subdecoders for *additional* matches,
# *ONLY* after "pattern" has *ALSO* been matched against.
'sv_cr_out': SVEXTRA,
'ldst_len': LdstLen,
'upd': LDSTMode,
- 'rc_sel': RC,
+ 'rc_sel': RCOE,
'cry_in': CryIn
}
'cr_out': 'CR out',
'ldst_len': 'ldst len',
'upd': 'upd',
+ 'rsrv': 'rsrv', # atomic operation
'rc_sel': 'rc',
'cry_in': 'cry in',
}
row_subset=None, conditions=None):
if conditions is None:
# XXX conditions = {}
- conditions = {'SVP64BREV': Const(0, 1),
+ conditions = {
'SVP64FFT': Const(0, 1),
}
self.actually_does_something = False
"""create_pdecode - creates a cascading hierarchical POWER ISA decoder
subsetting of the PowerOp decoding is possible by setting col_subset
+
+ NOTE (sigh) the bitsel patterns are in LSB0 order, they should be MSB0
"""
log("create_pdecode", name, col_subset, row_subset, include_fp)
pminor = [
m19,
Subdecoder(pattern=30, opcodes=get_csv("minor_30.csv"),
- opint=True, bitsel=(1, 5), suffix=None, subdecoders=[]),
+ opint=False, bitsel=(1, 5), suffix=None, subdecoders=[]),
Subdecoder(pattern=31, opcodes=get_csv("minor_31.csv"),
opint=True, bitsel=(1, 11), suffix=0b00101, subdecoders=[]),
Subdecoder(pattern=58, opcodes=get_csv("minor_58.csv"),
Subdecoder(pattern=62, opcodes=get_csv("minor_62.csv"),
opint=True, bitsel=(0, 2), suffix=None, subdecoders=[]),
Subdecoder(pattern=22, opcodes=get_csv("minor_22.csv"),
- opint=True, bitsel=(1, 5), suffix=None, subdecoders=[]),
+ opint=False, bitsel=(0, 11), suffix=None, subdecoders=[]),
Subdecoder(pattern=5, opcodes=get_csv("minor_5.csv"),
opint=True, bitsel=(0, 11), suffix=None, subdecoders=[]),
]
log("row_subset", opcode, row)
return row['unit'] in ['LDST', 'FPU']
- conditions = {'SVP64BREV': Signal(name="svp64brev", reset_less=True),
+ conditions = {
'SVP64FFT': Signal(name="svp64fft", reset_less=True),
}
pdecode = create_pdecode(name="rowsub",