power_insn: stricter reg type check

[openpower-isa.git] / src / openpower / decoder / power_decoder.py

diff --git a/src/openpower/decoder/power_decoder.py b/src/openpower/decoder/power_decoder.py
index 7e629632b7f756342714da9603d821ca1f850f0b..5ef452c6004ac48d8ab24b44ba4d67b5eb49ae92 100644 (file)
--- a/src/openpower/decoder/power_decoder.py
+++ b/src/openpower/decoder/power_decoder.py
@@ -94,7 +94,7 @@ from nmigen.cli import rtlil, verilog
 from openpower.decoder.power_enums import (Function, Form, MicrOp,
                                            In1Sel, In2Sel, In3Sel, OutSel,
                                            SVEXTRA, SVEtype, SVPtype, # Simple-V
-                                           RC, LdstLen, LDSTMode, CryIn,
+                                           RCOE, LdstLen, LDSTMode, CryIn,
                                            single_bit_flags, CRInSel,
                                            CROutSel, get_signal_name,
                                            default_values, insns, asmidx,
@@ -140,7 +140,7 @@ power_op_types = {'function_unit': Function,
                   'sv_cr_out': SVEXTRA,
                   'ldst_len': LdstLen,
                   'upd': LDSTMode,
-                  'rc_sel': RC,
+                  'rc_sel': RCOE,
                   'cry_in': CryIn
                   }
 
@@ -729,7 +729,7 @@ def create_pdecode(name=None, col_subset=None, row_subset=None,
     pminor = [
         m19,
         Subdecoder(pattern=30, opcodes=get_csv("minor_30.csv"),
-                   opint=True, bitsel=(1, 5), suffix=None, subdecoders=[]),
+                   opint=False, bitsel=(1, 5), suffix=None, subdecoders=[]),
         Subdecoder(pattern=31, opcodes=get_csv("minor_31.csv"),
                    opint=True, bitsel=(1, 11), suffix=0b00101, subdecoders=[]),
         Subdecoder(pattern=58, opcodes=get_csv("minor_58.csv"),