FastRegsEnum, XERRegsEnum, TT)
from openpower.state import CoreState
-from openpower.util import (spr_to_fast, log)
+from openpower.util import (spr_to_fast, spr_to_state, log)
def decode_spr_num(spr):
self.spr_i = Signal(10, reset_less=True)
self.spr_o = Data(SPR, name="spr_o")
- self.fast_o = Data(3, name="fast_o")
+ self.fast_o = Data(4, name="fast_o")
+ self.state_o = Data(3, name="state_o")
def elaborate(self, platform):
m = Module()
with m.Case(x.value):
m.d.comb += self.fast_o.data.eq(v)
m.d.comb += self.fast_o.ok.eq(1)
+ for x, v in spr_to_state.items():
+ with m.Case(x.value):
+ m.d.comb += self.state_o.data.eq(v)
+ m.d.comb += self.state_o.ok.eq(1)
return m
self.insn_in = Signal(32, reset_less=True)
self.reg_out = Data(5, name="reg_a")
self.spr_out = Data(SPR, "spr_a")
- self.fast_out = Data(3, "fast_a")
+ self.fast_out = Data(4, "fast_a")
+ self.state_out = Data(3, "state_a")
self.sv_nz = Signal(1)
def elaborate(self, platform):
comb += sprmap.spr_i.eq(spr)
comb += self.spr_out.eq(sprmap.spr_o)
comb += self.fast_out.eq(sprmap.fast_o)
+ comb += self.state_out.eq(sprmap.state_o)
return m
self.insn_in = Signal(32, reset_less=True)
self.reg_out = Data(7, "reg_b")
self.reg_isvec = Signal(1, name="reg_b_isvec") # TODO: in reg_out
- self.fast_out = Data(3, "fast_b")
+ self.fast_out = Data(4, "fast_b")
def elaborate(self, platform):
m = Module()
with m.Case(In2Sel.CONST_SH32): # unsigned - for shift
comb += self.imm_out.data.eq(self.dec.SH32)
comb += self.imm_out.ok.eq(1)
+ with m.Case(In2Sel.CONST_XBI): # unsigned - for grevi
+ comb += self.imm_out.data.eq(self.dec.FormXB.XBI)
+ comb += self.imm_out.ok.eq(1)
return m
self.insn_in = Signal(32, reset_less=True)
self.reg_out = Data(5, "reg_o")
self.spr_out = Data(SPR, "spr_o")
- self.fast_out = Data(3, "fast_o")
+ self.fast_out = Data(4, "fast_o")
+ self.state_out = Data(3, "state_o")
def elaborate(self, platform):
m = Module()
comb += sprmap.spr_i.eq(spr)
comb += self.spr_out.eq(sprmap.spr_o)
comb += self.fast_out.eq(sprmap.fast_o)
+ comb += self.state_out.eq(sprmap.state_o)
# determine Fast Reg
with m.Switch(op.internal_op):
self.insn_in = Signal(32, reset_less=True)
self.reg_out = Data(5, "reg_o2")
self.fp_madd_en = Signal(reset_less=True) # FFT instruction detected
- self.fast_out = Data(3, "fast_o2")
- self.fast_out3 = Data(3, "fast_o3")
+ self.fast_out = Data(4, "fast_o2")
+ self.fast_out3 = Data(4, "fast_o3")
def elaborate(self, platform):
m = Module()
MicrOp.OP_SHL, MicrOp.OP_SHR, MicrOp.OP_RLC,
MicrOp.OP_LOAD, MicrOp.OP_STORE,
MicrOp.OP_RLCL, MicrOp.OP_RLCR,
- MicrOp.OP_EXTSWSLI):
+ MicrOp.OP_EXTSWSLI, MicrOp.OP_GREV, MicrOp.OP_TERNLOG):
pass
# all other ops decode OE field
'is_signed': 'sgn',
'lk': 'lk',
'data_len': 'ldst_len',
+ 'reserve': 'rsrv',
'byte_reverse': 'br',
'sign_extend': 'sgn_ext',
'ldst_mode': 'upd',
comb += self.do_copy("byte_reverse", self.op_get("br"))
comb += self.do_copy("sign_extend", self.op_get("sgn_ext"))
comb += self.do_copy("ldst_mode", self.op_get("upd")) # LD/ST mode
+ comb += self.do_copy("reserve", self.op_get("rsrv")) # atomic
# copy over SVP64 input record fields (if they exist)
if self.svp64_en:
to make this work, TestIssuer must notice "exception.happened"
after the (failed) LD/ST and copies the LDSTException info from
the output, into here (PowerDecoder2). without incrementing PC.
+
+ also instr_fault works the same way: the instruction is "rewritten"
+ so that the "fake" op that gets created is OP_FETCH_FAILED
"""
def __init__(self, dec, opkls=None, fn_name=None, final=False,
state=None, svp64_en=True, regreduce_en=False):
super().__init__(dec, opkls, fn_name, final, state, svp64_en,
regreduce_en=False)
- self.ldst_exc = LDSTException("dec2_exc")
+ self.ldst_exc = LDSTException("dec2_exc") # rewrites as OP_TRAP
+ self.instr_fault = Signal() # rewrites instruction as OP_FETCH_FAILED
if self.svp64_en:
self.cr_out_isvec = Signal(1, name="cr_out_isvec")
# TODO add SPRs here. must be True when *all* are scalar
l = map(lambda svdec: svdec.isvec, [in1_svdec, in2_svdec, in3_svdec,
- crin_svdec, crin_svdec_b, crin_svdec_o])
+ crin_svdec, crin_svdec_b,
+ crin_svdec_o])
comb += self.no_in_vec.eq(~Cat(*l).bool()) # all input scalar
l = map(lambda svdec: svdec.isvec, [
o2_svdec, o_svdec, crout_svdec])
comb += e.write_fast1.eq(dec_o.fast_out) # SRR0 (OP_RFID)
comb += e.write_fast2.eq(dec_o2.fast_out) # SRR1 (ditto)
comb += e.write_fast3.eq(dec_o2.fast_out3) # SVSRR0 (ditto)
+ # and State regs (DEC, TB)
+ comb += e.read_state1.eq(dec_a.state_out) # DEC/TB
+ comb += e.write_state1.eq(dec_o.state_out) # DEC/TB
# sigh this is exactly the sort of thing for which the
# decoder is designed to not need. MTSPR, MFSPR and others need
comb += priv_ok.eq(is_priv_insn & msr[MSR.PR])
comb += illeg_ok.eq(op.internal_op == MicrOp.OP_ILLEGAL)
+ # absolute top priority: check for an instruction failed
+ with m.If(self.instr_fault):
+ comb += self.e.eq(0) # reset eeeeeverything
+ comb += self.do_copy("insn", self.dec.opcode_in, True)
+ comb += self.do_copy("insn_type", MicrOp.OP_FETCH_FAILED, True)
+ comb += self.do_copy("fn_unit", Function.MMU, True)
+ comb += self.do_copy("cia", self.state.pc, True) # PC
+ comb += self.do_copy("msr", self.state.msr, True) # MSR
+ # special override on internal_op, due to being a "fake" op
+ comb += self.dec.op.internal_op.eq(MicrOp.OP_FETCH_FAILED)
+
# LD/ST exceptions. TestIssuer copies the exception info at us
# after a failed LD/ST.
- with m.If(ldst_exc.happened):
+ with m.Elif(ldst_exc.happened):
with m.If(ldst_exc.alignment):
- self.trap(m, TT.PRIV, 0x600)
+ self.trap(m, TT.MEMEXC, 0x600)
with m.Elif(ldst_exc.instr_fault):
with m.If(ldst_exc.segment_fault):
- self.trap(m, TT.PRIV, 0x480)
+ self.trap(m, TT.MEMEXC, 0x480)
with m.Else():
# pass exception info to trap to create SRR1
self.trap(m, TT.MEMEXC, 0x400, ldst_exc)
with m.Else():
with m.If(ldst_exc.segment_fault):
- self.trap(m, TT.PRIV, 0x380)
+ self.trap(m, TT.MEMEXC, 0x380)
with m.Else():
- self.trap(m, TT.PRIV, 0x300)
+ self.trap(m, TT.MEMEXC, 0x300)
# decrement counter (v3.0B p1099): TODO 32-bit version (MSR.LPCR)
with m.Elif(dec_irq_ok):
projects / openpower-isa.git / blobdiff