from openpower.decoder.power_svp64_prefix import SVP64PrefixDecoder
from openpower.decoder.power_svp64_extra import SVP64CRExtra, SVP64RegExtra
-from openpower.decoder.power_svp64_rm import SVP64RMModeDecode
+from openpower.decoder.power_svp64_rm import (SVP64RMModeDecode,
+ sv_input_record_layout,
+ SVP64RMMode)
+from openpower.sv.svp64 import SVP64Rec
+
from openpower.decoder.power_regspec_map import regspec_decode_read
-from openpower.decoder.power_regspec_map import regspec_decode_write
-from openpower.decoder.power_decoder import create_pdecode
+from openpower.decoder.power_decoder import (create_pdecode,
+ create_pdecode_svp64_ldst,
+ PowerOp)
from openpower.decoder.power_enums import (MicrOp, CryIn, Function,
CRInSel, CROutSel,
LdstLen, In1Sel, In2Sel, In3Sel,
OutSel, SPRfull, SPRreduced,
- RC, LDSTMode,
+ RC, SVP64LDSTmode, LDSTMode,
SVEXTRA, SVEtype, SVPtype)
from openpower.decoder.decode2execute1 import (Decode2ToExecute1Type, Data,
- Decode2ToOperand)
-from openpower.sv.svp64 import SVP64Rec
+ Decode2ToOperand)
+
from openpower.consts import (MSR, SPEC, EXTRA2, EXTRA3, SVP64P, field,
- SPEC_SIZE, SPECb, SPEC_AUG_SIZE, SVP64CROffs)
+ SPEC_SIZE, SPECb, SPEC_AUG_SIZE, SVP64CROffs,
+ FastRegsEnum, XERRegsEnum, TT)
-from openpower.consts import FastRegsEnum
-from openpower.consts import XERRegsEnum
-from openpower.consts import TT
from openpower.state import CoreState
-from openpower.util import spr_to_fast
+from openpower.util import (spr_to_fast, log)
def decode_spr_num(spr):
decodes register RA, implicit and explicit CSRs
"""
- def __init__(self, dec, regreduce_en):
+ def __init__(self, dec, op, regreduce_en):
self.regreduce_en = regreduce_en
if self.regreduce_en:
SPR = SPRreduced
else:
SPR = SPRfull
self.dec = dec
+ self.op = op
self.sel_in = Signal(In1Sel, reset_less=True)
self.insn_in = Signal(32, reset_less=True)
self.reg_out = Data(5, name="reg_a")
def elaborate(self, platform):
m = Module()
comb = m.d.comb
- op = self.dec.op
+ op = self.op
reg = self.reg_out
m.submodules.sprmap = sprmap = SPRMap(self.regreduce_en)
comb += reg.data.eq(rs)
comb += reg.ok.eq(1)
+ # select Register FRA field,
+ fra = Signal(5, reset_less=True)
+ comb += fra.eq(self.dec.FRA)
+ with m.If(self.sel_in == In1Sel.FRA):
+ comb += reg.data.eq(fra)
+ comb += reg.ok.eq(1)
+
+ # select Register FRS field,
+ frs = Signal(5, reset_less=True)
+ comb += frs.eq(self.dec.FRS)
+ with m.If(self.sel_in == In1Sel.FRS):
+ comb += reg.data.eq(frs)
+ comb += reg.ok.eq(1)
+
# decode Fast-SPR based on instruction type
with m.Switch(op.internal_op):
immediates are muxed in.
"""
- def __init__(self, dec):
+ def __init__(self, dec, op):
self.dec = dec
+ self.op = op
self.sel_in = Signal(In2Sel, reset_less=True)
self.insn_in = Signal(32, reset_less=True)
self.reg_out = Data(7, "reg_b")
def elaborate(self, platform):
m = Module()
comb = m.d.comb
- op = self.dec.op
+ op = self.op
reg = self.reg_out
# select Register B field
with m.Switch(self.sel_in):
+ with m.Case(In2Sel.FRB):
+ comb += reg.data.eq(self.dec.FRB)
+ comb += reg.ok.eq(1)
with m.Case(In2Sel.RB):
comb += reg.data.eq(self.dec.RB)
comb += reg.ok.eq(1)
decodes register RC. this is "lane 3" into some CompUnits (not many)
"""
- def __init__(self, dec):
+ def __init__(self, dec, op):
self.dec = dec
+ self.op = op
self.sel_in = Signal(In3Sel, reset_less=True)
self.insn_in = Signal(32, reset_less=True)
self.reg_out = Data(5, "reg_c")
def elaborate(self, platform):
m = Module()
comb = m.d.comb
- op = self.dec.op
+ op = self.op
reg = self.reg_out
# select Register C field
# for M-Form shiftrot
comb += reg.data.eq(self.dec.RB)
comb += reg.ok.eq(1)
+ with m.Case(In3Sel.FRS):
+ comb += reg.data.eq(self.dec.FRS)
+ comb += reg.ok.eq(1)
+ with m.Case(In3Sel.FRC):
+ comb += reg.data.eq(self.dec.FRC)
+ comb += reg.ok.eq(1)
with m.Case(In3Sel.RS):
comb += reg.data.eq(self.dec.RS)
comb += reg.ok.eq(1)
+ with m.Case(In3Sel.RC):
+ comb += reg.data.eq(self.dec.RC)
+ comb += reg.ok.eq(1)
return m
decodes output register RA, RT or SPR
"""
- def __init__(self, dec, regreduce_en):
+ def __init__(self, dec, op, regreduce_en):
self.regreduce_en = regreduce_en
if self.regreduce_en:
SPR = SPRreduced
else:
SPR = SPRfull
self.dec = dec
+ self.op = op
self.sel_in = Signal(OutSel, reset_less=True)
self.insn_in = Signal(32, reset_less=True)
self.reg_out = Data(5, "reg_o")
m = Module()
comb = m.d.comb
m.submodules.sprmap = sprmap = SPRMap(self.regreduce_en)
- op = self.dec.op
+ op = self.op
reg = self.reg_out
# select Register out field
with m.Switch(self.sel_in):
+ with m.Case(OutSel.FRT):
+ comb += reg.data.eq(self.dec.FRT)
+ comb += reg.ok.eq(1)
with m.Case(OutSel.RT):
comb += reg.data.eq(self.dec.RT)
comb += reg.ok.eq(1)
but there are others.
"""
- def __init__(self, dec):
+ def __init__(self, dec, op):
self.dec = dec
+ self.op = op
self.sel_in = Signal(OutSel, reset_less=True)
self.lk = Signal(reset_less=True)
self.insn_in = Signal(32, reset_less=True)
self.reg_out = Data(5, "reg_o2")
self.fast_out = Data(3, "fast_o2")
+ self.fast_out3 = Data(3, "fast_o3")
def elaborate(self, platform):
m = Module()
comb = m.d.comb
- op = self.dec.op
+ op = self.op
#m.submodules.svdec = svdec = SVP64RegExtra()
# get the 5-bit reg data before svp64-munging it into 7-bit plus isvec
#reg = Signal(5, reset_less=True)
- if hasattr(self.dec.op, "upd"):
+ if hasattr(op, "upd"):
# update mode LD/ST uses read-reg A also as an output
- with m.If(self.dec.op.upd == LDSTMode.update):
+ with m.If(op.upd == LDSTMode.update):
comb += self.reg_out.data.eq(self.dec.RA)
comb += self.reg_out.ok.eq(1)
comb += self.fast_out.data.eq(FastRegsEnum.LR) # LR
comb += self.fast_out.ok.eq(1)
- # RFID 2nd spr (fast)
+ # RFID 2nd and 3rd spr (fast)
with m.Case(MicrOp.OP_RFID):
comb += self.fast_out.data.eq(FastRegsEnum.SRR1) # SRR1
comb += self.fast_out.ok.eq(1)
+ comb += self.fast_out3.data.eq(FastRegsEnum.SVSRR0) # SVSRR0
+ comb += self.fast_out3.ok.eq(1)
return m
-- test that further down when assigning to the multiplier oe input.
"""
- def __init__(self, dec):
+ def __init__(self, dec, op):
self.dec = dec
+ self.op = op
self.sel_in = Signal(RC, reset_less=True)
self.insn_in = Signal(32, reset_less=True)
self.oe_out = Data(1, "oe")
def elaborate(self, platform):
m = Module()
comb = m.d.comb
- op = self.dec.op
+ op = self.op
with m.Switch(op.internal_op):
bits because they refer to CR0-CR7
"""
- def __init__(self, dec):
+ def __init__(self, dec, op):
self.dec = dec
+ self.op = op
self.sel_in = Signal(CRInSel, reset_less=True)
self.insn_in = Signal(32, reset_less=True)
self.cr_bitfield = Data(3, "cr_bitfield")
def elaborate(self, platform):
m = Module()
comb = m.d.comb
- op = self.dec.op
+ op = self.op
m.submodules.ppick = ppick = PriorityPicker(8, reverse_i=True,
reverse_o=True)
bits because they refer to CR0-CR7
"""
- def __init__(self, dec):
+ def __init__(self, dec, op):
self.dec = dec
+ self.op = op
self.rc_in = Signal(reset_less=True)
self.sel_in = Signal(CROutSel, reset_less=True)
self.insn_in = Signal(32, reset_less=True)
def elaborate(self, platform):
m = Module()
comb = m.d.comb
- op = self.dec.op
+ op = self.op
m.submodules.ppick = ppick = PriorityPicker(8, reverse_i=True,
reverse_o=True)
# to be decoded (this includes the single bit names)
record_names = {'insn_type': 'internal_op',
'fn_unit': 'function_unit',
+ 'SV_Ptype': 'SV_Ptype',
'rc': 'rc_sel',
'oe': 'rc_sel',
'zero_a': 'in1_sel',
self.svp64_en = svp64_en
self.regreduce_en = regreduce_en
if svp64_en:
+ self.is_svp64_mode = Signal() # mark decoding as SVP64 Mode
+ self.use_svp64_ldst_dec = Signal() # must use LDST decoder
self.sv_rm = SVP64Rec(name="dec_svp64") # SVP64 RM field
+ self.rm_dec = SVP64RMModeDecode("svp64_rm_dec")
+ # set these to the predicate mask bits needed for the ALU
+ self.pred_sm = Signal() # TODO expand to SIMD mask width
+ self.pred_dm = Signal() # TODO expand to SIMD mask width
self.sv_a_nz = Signal(1)
self.final = final
self.opkls = opkls
row_subset=self.rowsubsetfn)
self.dec = dec
+ # create SVP64 LDST decoder
+ if svp64_en and (not final or fn_name.lower().startswith("ldst")):
+ if fn_name:
+ name = "sv_"+fn_name
+ else:
+ name = "svdec"
+ svdecldst = create_pdecode_svp64_ldst(name=name,
+ col_subset=col_subset,
+ row_subset=self.rowsubsetfn)
+ self.svdecldst = svdecldst
+ else:
+ self.svdecldst = None
+
+ # set up a copy of the PowerOp
+ self.op = PowerOp.like(self.dec.op)
+
# state information needed by the Decoder
if state is None:
state = CoreState("dec2")
for k, v in record_names.items():
if hasattr(do, k):
subset.add(v)
- print ("get_col_subset", self.fn_name, do.fields, subset)
+ log ("get_col_subset", self.fn_name, do.fields, subset)
return subset
def rowsubsetfn(self, opcode, row):
ports = self.dec.ports() + self.e.ports()
if self.svp64_en:
ports += self.sv_rm.ports()
+ if self.svdecldst:
+ ports += self.svdecldst.ports()
return ports
def needs_field(self, field, op_field):
do = self.e_tmp.do
return hasattr(do, field) and self.op_get(op_field) is not None
- def do_copy(self, field, val, final=False):
+ def do_get(self, field, final=False):
if final or self.final:
do = self.do
else:
do = self.e_tmp.do
- if hasattr(do, field) and val is not None:
- return getattr(do, field).eq(val)
+ return getattr(do, field, None)
+
+ def do_copy(self, field, val, final=False):
+ df = self.do_get(field, final)
+ if df is not None and val is not None:
+ return df.eq(val)
return []
def op_get(self, op_field):
- return getattr(self.dec.op, op_field, None)
+ return getattr(self.op, op_field, None)
def elaborate(self, platform):
if self.regreduce_en:
comb = m.d.comb
state = self.state
op, do = self.dec.op, self.do
- msr, cia = state.msr, state.pc
+ msr, cia, svstate = state.msr, state.pc, state.svstate
# fill in for a normal instruction (not an exception)
# copy over if non-exception, non-privileged etc. is detected
if not self.final:
# set up submodule decoders
m.submodules.dec = self.dec
m.submodules.dec_rc = self.dec_rc = dec_rc = DecodeRC(self.dec)
- m.submodules.dec_oe = dec_oe = DecodeOE(self.dec)
+ m.submodules.dec_oe = dec_oe = DecodeOE(self.dec, op)
+
+ # use op from first decoder (self.dec.op) if not in SVP64-LDST mode
+ # (TODO)
+ comb += self.op.eq(self.dec.op)
+
+ if self.svp64_en:
+ # and SVP64 RM mode decoder
+ m.submodules.sv_rm_dec = rm_dec = self.rm_dec
+ if self.svdecldst:
+ # and SVP64 decoder
+ m.submodules.svdecldst = svdecldst = self.svdecldst
# copy instruction through...
for i in [do.insn, dec_rc.insn_in, dec_oe.insn_in, ]:
comb += i.eq(self.dec.opcode_in)
# ...and subdecoders' input fields
- comb += dec_rc.sel_in.eq(op.rc_sel)
- comb += dec_oe.sel_in.eq(op.rc_sel) # XXX should be OE sel
+ comb += dec_rc.sel_in.eq(self.op_get("rc_sel"))
+ comb += dec_oe.sel_in.eq(self.op_get("rc_sel")) # XXX should be OE sel
# copy "state" over
comb += self.do_copy("msr", msr)
comb += self.do_copy("cia", cia)
+ comb += self.do_copy("svstate", svstate)
# set up instruction type
# no op: defaults to OP_ILLEGAL
if self.needs_field("zero_a", "in1_sel"):
m.submodules.dec_ai = dec_ai = DecodeAImm(self.dec)
comb += dec_ai.sv_nz.eq(self.sv_a_nz)
- comb += dec_ai.sel_in.eq(op.in1_sel)
+ comb += dec_ai.sel_in.eq(self.op_get("in1_sel"))
comb += self.do_copy("zero_a", dec_ai.immz_out) # RA==0 detected
if self.needs_field("imm_data", "in2_sel"):
m.submodules.dec_bi = dec_bi = DecodeBImm(self.dec)
- comb += dec_bi.sel_in.eq(op.in2_sel)
+ comb += dec_bi.sel_in.eq(self.op_get("in2_sel"))
comb += self.do_copy("imm_data", dec_bi.imm_out) # imm in RB
# rc and oe out
# CR in/out - note: these MUST match with what happens in
# DecodeCROut!
rc_out = self.dec_rc.rc_out.data
- with m.Switch(op.cr_out):
+ with m.Switch(self.op_get("cr_out")):
with m.Case(CROutSel.CR0, CROutSel.CR1):
comb += self.do_copy("write_cr0", rc_out) # only when RC=1
with m.Case(CROutSel.BF, CROutSel.BT):
comb += self.do_copy("input_cr", self.op_get("cr_in")) # CR in
comb += self.do_copy("output_cr", self.op_get("cr_out")) # CR out
+ if self.svp64_en:
+ # connect up SVP64 RM Mode decoding. however... we need a shorter
+ # path, for the LDST bit-reverse detection. so perform partial
+ # decode when SVP64 is detected. then, bit-reverse mode can be
+ # quickly determined, and the Decoder result MUXed over to
+ # the alternative decoder, svdecldst. what a mess... *sigh*
+ sv_ptype = self.op_get("SV_Ptype")
+ fn = self.op_get("function_unit")
+ # detect major opcode for LDs: include 58 here. from CSV files.
+ is_major_ld = Signal()
+ major = Signal(6) # bits... errr... MSB0 0..5 which is 26:32 python
+ comb += major.eq(self.dec.opcode_in[26:32])
+ comb += is_major_ld.eq((major == 34) | (major == 35) |
+ (major == 50) | (major == 51) |
+ (major == 48) | (major == 49) |
+ (major == 42) | (major == 43) |
+ (major == 40) | (major == 41) |
+ (major == 32) | (major == 33) |
+ (major == 58))
+ with m.If(self.is_svp64_mode & is_major_ld):
+ # straight-up: "it's a LD"
+ comb += rm_dec.fn_in.eq(Function.LDST)
+ with m.Else():
+ comb += rm_dec.fn_in.eq(fn) # decode needs to know Fn type
+ comb += rm_dec.ptype_in.eq(sv_ptype) # Single/Twin predicated
+ comb += rm_dec.rc_in.eq(rc_out) # Rc=1
+ comb += rm_dec.rm_in.eq(self.sv_rm) # SVP64 RM mode
+ if self.needs_field("imm_data", "in2_sel"):
+ bzero = dec_bi.imm_out.ok & ~dec_bi.imm_out.data.bool()
+ comb += rm_dec.ldst_imz_in.eq(bzero) # B immediate is zero
+ # main PowerDecoder2 determines if bit-reverse mode requested
+ if not self.final:
+ bitrev = rm_dec.ldstmode == SVP64LDSTmode.BITREVERSE
+ comb += self.use_svp64_ldst_dec.eq(bitrev)
+
# decoded/selected instruction flags
comb += self.do_copy("data_len", self.op_get("ldst_len"))
comb += self.do_copy("invert_in", self.op_get("inv_a"))
comb += self.do_copy("sign_extend", self.op_get("sgn_ext"))
comb += self.do_copy("ldst_mode", self.op_get("upd")) # LD/ST mode
+ # copy over SVP64 input record fields (if they exist)
+ if self.svp64_en:
+ # TODO, really do we have to do these explicitly?? sigh
+ #for (field, _) in sv_input_record_layout:
+ # comb += self.do_copy(field, self.rm_dec.op_get(field))
+ comb += self.do_copy("sv_saturate", self.rm_dec.saturate)
+ comb += self.do_copy("sv_Ptype", self.rm_dec.ptype_in)
+ comb += self.do_copy("sv_ldstmode", self.rm_dec.ldstmode)
+ # these get set up based on incoming mask bits. TODO:
+ # pass in multiple bits (later, when SIMD backends are enabled)
+ with m.If(self.rm_dec.pred_sz):
+ comb += self.do_copy("sv_pred_sz", ~self.pred_sm)
+ with m.If(self.rm_dec.pred_dz):
+ comb += self.do_copy("sv_pred_dz", ~self.pred_dm)
+
return m
state=None, svp64_en=True, regreduce_en=False):
super().__init__(dec, opkls, fn_name, final, state, svp64_en,
regreduce_en=False)
- self.exc = LDSTException("dec2_exc")
+ self.ldst_exc = LDSTException("dec2_exc")
if self.svp64_en:
self.cr_out_isvec = Signal(1, name="cr_out_isvec")
self.no_in_vec = Signal(1, name="no_in_vec") # no inputs vector
self.no_out_vec = Signal(1, name="no_out_vec") # no outputs vector
self.loop_continue = Signal(1, name="loop_continue")
- self.rm_dec = SVP64RMModeDecode("svp64_rm_dec")
else:
self.no_in_vec = Const(1, 1)
self.no_out_vec = Const(1, 1)
subset.add("sv_cr_out")
subset.add("SV_Etype")
subset.add("SV_Ptype")
+ # from SVP64RMModeDecode
+ for (field, _) in sv_input_record_layout:
+ subset.add(field)
subset.add("lk")
subset.add("internal_op")
subset.add("form")
m = super().elaborate(platform)
comb = m.d.comb
state = self.state
- e_out, op, do_out = self.e, self.dec.op, self.e.do
+ op, e_out, do_out = self.op, self.e, self.e.do
dec_spr, msr, cia, ext_irq = state.dec, state.msr, state.pc, state.eint
rc_out = self.dec_rc.rc_out.data
e = self.e_tmp
# copy over if non-exception, non-privileged etc. is detected
# set up submodule decoders
- m.submodules.dec_a = dec_a = DecodeA(self.dec, self.regreduce_en)
- m.submodules.dec_b = dec_b = DecodeB(self.dec)
- m.submodules.dec_c = dec_c = DecodeC(self.dec)
- m.submodules.dec_o = dec_o = DecodeOut(self.dec, self.regreduce_en)
- m.submodules.dec_o2 = dec_o2 = DecodeOut2(self.dec)
- m.submodules.dec_cr_in = self.dec_cr_in = DecodeCRIn(self.dec)
- m.submodules.dec_cr_out = self.dec_cr_out = DecodeCROut(self.dec)
+ m.submodules.dec_a = dec_a = DecodeA(self.dec, op, self.regreduce_en)
+ m.submodules.dec_b = dec_b = DecodeB(self.dec, op)
+ m.submodules.dec_c = dec_c = DecodeC(self.dec, op)
+ m.submodules.dec_o = dec_o = DecodeOut(self.dec, op, self.regreduce_en)
+ m.submodules.dec_o2 = dec_o2 = DecodeOut2(self.dec, op)
+ m.submodules.dec_cr_in = self.dec_cr_in = DecodeCRIn(self.dec, op)
+ m.submodules.dec_cr_out = self.dec_cr_out = DecodeCROut(self.dec, op)
comb += dec_a.sv_nz.eq(self.sv_a_nz)
if self.svp64_en:
# debug access to crout_svdec (used in get_pdecode_cr_out)
self.crout_svdec = crout_svdec
- # and SVP64 RM mode decoder
- m.submodules.sv_rm_dec = rm_dec = self.rm_dec
-
# get the 5-bit reg data before svp64-munging it into 7-bit plus isvec
reg = Signal(5, reset_less=True)
comb += i.eq(self.dec.opcode_in)
# CR setup
- comb += self.dec_cr_in.sel_in.eq(op.cr_in)
- comb += self.dec_cr_out.sel_in.eq(op.cr_out)
+ comb += self.dec_cr_in.sel_in.eq(self.op_get("cr_in"))
+ comb += self.dec_cr_out.sel_in.eq(self.op_get("cr_out"))
comb += self.dec_cr_out.rc_in.eq(rc_out)
# CR register info
comb += self.do_copy("write_cr_whole", self.dec_cr_out.whole_reg)
# ...and subdecoders' input fields
- comb += dec_a.sel_in.eq(op.in1_sel)
- comb += dec_b.sel_in.eq(op.in2_sel)
- comb += dec_c.sel_in.eq(op.in3_sel)
- comb += dec_o.sel_in.eq(op.out_sel)
- comb += dec_o2.sel_in.eq(op.out_sel)
+ comb += dec_a.sel_in.eq(self.op_get("in1_sel"))
+ comb += dec_b.sel_in.eq(self.op_get("in2_sel"))
+ comb += dec_c.sel_in.eq(self.op_get("in3_sel"))
+ comb += dec_o.sel_in.eq(self.op_get("out_sel"))
+ comb += dec_o2.sel_in.eq(self.op_get("out_sel"))
if hasattr(do, "lk"):
comb += dec_o2.lk.eq(do.lk)
#######
# CR out
- comb += crout_svdec.idx.eq(op.sv_cr_out) # SVP64 CR out
+ comb += crout_svdec.idx.eq(self.op_get("sv_cr_out")) # SVP64 CR out
comb += self.cr_out_isvec.eq(crout_svdec.isvec)
#######
# these change slightly, when decoding BA/BB. really should have
# their own separate CSV column: sv_cr_in1 and sv_cr_in2, but hey
- comb += cr_a_idx.eq(op.sv_cr_in)
+ comb += cr_a_idx.eq(self.op_get("sv_cr_in"))
comb += cr_b_idx.eq(SVEXTRA.NONE)
- with m.If(op.sv_cr_in == SVEXTRA.Idx_1_2.value):
+ with m.If(self.op_get("sv_cr_in") == SVEXTRA.Idx_1_2.value):
comb += cr_a_idx.eq(SVEXTRA.Idx1)
comb += cr_b_idx.eq(SVEXTRA.Idx2)
# indices are slightly different, BA/BB mess sorted above
comb += crin_svdec.idx.eq(cr_a_idx) # SVP64 CR in A
comb += crin_svdec_b.idx.eq(cr_b_idx) # SVP64 CR in B
- comb += crin_svdec_o.idx.eq(op.sv_cr_out) # SVP64 CR out
+ comb += crin_svdec_o.idx.eq(self.op_get("sv_cr_out")) # SVP64 CR out
# get SVSTATE srcstep (TODO: elwidth etc.) needed below
+ vl = Signal.like(self.state.svstate.vl)
srcstep = Signal.like(self.state.svstate.srcstep)
dststep = Signal.like(self.state.svstate.dststep)
+ comb += vl.eq(self.state.svstate.vl)
comb += srcstep.eq(self.state.svstate.srcstep)
comb += dststep.eq(self.state.svstate.dststep)
# registers a, b, c and out and out2 (LD/ST EA)
+ sv_etype = self.op_get("SV_Etype")
for to_reg, fromreg, svdec, out in (
(e.read_reg1, dec_a.reg_out, in1_svdec, False),
(e.read_reg2, dec_b.reg_out, in2_svdec, False),
(e.read_reg3, dec_c.reg_out, in3_svdec, False),
(e.write_reg, dec_o.reg_out, o_svdec, True),
(e.write_ea, dec_o2.reg_out, o2_svdec, True)):
- comb += svdec.extra.eq(extra) # EXTRA field of SVP64 RM
- comb += svdec.etype.eq(op.SV_Etype) # EXTRA2/3 for this insn
+ comb += svdec.extra.eq(extra) # EXTRA field of SVP64 RM
+ comb += svdec.etype.eq(sv_etype) # EXTRA2/3 for this insn
comb += svdec.reg_in.eq(fromreg.data) # 3-bit (CR0/BC/BFA)
comb += to_reg.ok.eq(fromreg.ok)
# detect if Vectorised: add srcstep/dststep if yes.
# to_reg is 7-bits, outs get dststep added, ins get srcstep
with m.If(svdec.isvec):
step = dststep if out else srcstep
- comb += to_reg.data.eq(step+svdec.reg_out)
+ # reverse gear goes the opposite way
+ with m.If(self.rm_dec.reverse_gear):
+ comb += to_reg.data.eq(svdec.reg_out+(vl-1-step))
+ with m.Else():
+ comb += to_reg.data.eq(step+svdec.reg_out)
with m.Else():
comb += to_reg.data.eq(svdec.reg_out)
- comb += in1_svdec.idx.eq(op.sv_in1) # SVP64 reg #1 (in1_sel)
- comb += in2_svdec.idx.eq(op.sv_in2) # SVP64 reg #2 (in2_sel)
- comb += in3_svdec.idx.eq(op.sv_in3) # SVP64 reg #3 (in3_sel)
- comb += o_svdec.idx.eq(op.sv_out) # SVP64 output (out_sel)
- comb += o2_svdec.idx.eq(op.sv_out2) # SVP64 output (implicit)
+ # SVP64 in/out fields
+ comb += in1_svdec.idx.eq(self.op_get("sv_in1")) # reg #1 (in1_sel)
+ comb += in2_svdec.idx.eq(self.op_get("sv_in2")) # reg #2 (in2_sel)
+ comb += in3_svdec.idx.eq(self.op_get("sv_in3")) # reg #3 (in3_sel)
+ comb += o_svdec.idx.eq(self.op_get("sv_out")) # output (out_sel)
+ comb += o2_svdec.idx.eq(self.op_get("sv_out2")) # output (implicit)
# XXX TODO - work out where this should come from. the problem is
# that LD-with-update is implied (computed from "is instruction in
# "update mode" rather than specified cleanly as its own CSV column
crin_svdec, crin_svdec_b, crin_svdec_o])
comb += self.no_in_vec.eq(~Cat(*l).bool()) # all input scalar
l = map(lambda svdec: svdec.isvec, [o2_svdec, o_svdec, crout_svdec])
- comb += self.no_out_vec.eq(~Cat(*l).bool()) # all output scalar
+ # in mapreduce mode, scalar out is *allowed*
+ with m.If(self.rm_dec.mode == SVP64RMMode.MAPREDUCE.value):
+ comb += self.no_out_vec.eq(0)
+ with m.Else():
+ comb += self.no_out_vec.eq(~Cat(*l).bool()) # all output scalar
# now create a general-purpose "test" as to whether looping
# should continue. this doesn't include predication bit-tests
loop = self.loop_continue
- with m.Switch(op.SV_Ptype):
+ with m.Switch(self.op_get("SV_Ptype")):
with m.Case(SVPtype.P2.value):
# twin-predication
# TODO: *and cache-inhibited LD/ST!*
(e.read_cr3, self.dec_cr_in, "cr_bitfield_o", crin_svdec_o, 0),
(e.write_cr, self.dec_cr_out, "cr_bitfield", crout_svdec, 1)):
fromreg = getattr(cr, name)
- comb += svdec.extra.eq(extra) # EXTRA field of SVP64 RM
- comb += svdec.etype.eq(op.SV_Etype) # EXTRA2/3 for this insn
+ comb += svdec.extra.eq(extra) # EXTRA field of SVP64 RM
+ comb += svdec.etype.eq(sv_etype) # EXTRA2/3 for this insn
comb += svdec.cr_in.eq(fromreg.data) # 3-bit (CR0/BC/BFA)
with m.If(svdec.isvec):
# check if this is CR0 or CR1: treated differently
comb += to_reg.data.eq(fromreg.data)
comb += to_reg.ok.eq(fromreg.ok)
+ if self.svp64_en:
+ comb += self.rm_dec.ldst_ra_vec.eq(self.in1_isvec) # RA is vector
+
# SPRs out
comb += e.read_spr1.eq(dec_a.spr_out)
comb += e.write_spr.eq(dec_o.spr_out)
- # Fast regs out
+ # Fast regs out including SRR0/1/SVSRR0
comb += e.read_fast1.eq(dec_a.fast_out)
comb += e.read_fast2.eq(dec_b.fast_out)
- comb += e.write_fast1.eq(dec_o.fast_out)
- comb += e.write_fast2.eq(dec_o2.fast_out)
-
- if self.svp64_en:
- # connect up SVP64 RM Mode decoding
- fn = self.op_get("function_unit")
- comb += rm_dec.fn_in.eq(fn) # decode needs to know if LD/ST type
- comb += rm_dec.ptype_in.eq(op.SV_Ptype) # Single/Twin predicated
- comb += rm_dec.rc_in.eq(rc_out) # Rc=1
- comb += rm_dec.rm_in.eq(self.sv_rm) # SVP64 RM mode
+ comb += e.write_fast1.eq(dec_o.fast_out) # SRR0 (OP_RFID)
+ comb += e.write_fast2.eq(dec_o2.fast_out) # SRR1 (ditto)
+ comb += e.write_fast3.eq(dec_o2.fast_out3) # SVSRR0 (ditto)
# sigh this is exactly the sort of thing for which the
# decoder is designed to not need. MTSPR, MFSPR and others need
# access to the XER bits. however setting e.oe is not appropriate
- with m.If(op.internal_op == MicrOp.OP_MFSPR):
+ internal_op = self.op_get("internal_op")
+ with m.If(internal_op == MicrOp.OP_MFSPR):
comb += e.xer_in.eq(0b111) # SO, CA, OV
- with m.If(op.internal_op == MicrOp.OP_CMP):
+ with m.If(internal_op == MicrOp.OP_CMP):
comb += e.xer_in.eq(1<<XERRegsEnum.SO) # SO
- with m.If(op.internal_op == MicrOp.OP_MTSPR):
+ with m.If(internal_op == MicrOp.OP_MTSPR):
comb += e.xer_out.eq(1)
# set the trapaddr to 0x700 for a td/tw/tdi/twi operation
dec_irq_ok = Signal()
priv_ok = Signal()
illeg_ok = Signal()
- exc = self.exc
+ ldst_exc = self.ldst_exc
comb += ext_irq_ok.eq(ext_irq & msr[MSR.EE]) # v3.0B p944 (MSR.EE)
comb += dec_irq_ok.eq(dec_spr[63] & msr[MSR.EE]) # 6.5.11 p1076
# LD/ST exceptions. TestIssuer copies the exception info at us
# after a failed LD/ST.
- with m.If(exc.happened):
- with m.If(exc.alignment):
+ with m.If(ldst_exc.happened):
+ with m.If(ldst_exc.alignment):
self.trap(m, TT.PRIV, 0x600)
- with m.Elif(exc.instr_fault):
- with m.If(exc.segment_fault):
+ with m.Elif(ldst_exc.instr_fault):
+ with m.If(ldst_exc.segment_fault):
self.trap(m, TT.PRIV, 0x480)
with m.Else():
# pass exception info to trap to create SRR1
- self.trap(m, TT.MEMEXC, 0x400, exc)
+ self.trap(m, TT.MEMEXC, 0x400, ldst_exc)
with m.Else():
- with m.If(exc.segment_fault):
+ with m.If(ldst_exc.segment_fault):
self.trap(m, TT.PRIV, 0x380)
with m.Else():
self.trap(m, TT.PRIV, 0x300)
# TRAP write fast2 = SRR1
comb += e_out.write_fast2.data.eq(FastRegsEnum.SRR1) # SRR1
comb += e_out.write_fast2.ok.eq(1)
+ # TRAP write fast2 = SRR1
+ comb += e_out.write_fast3.data.eq(FastRegsEnum.SVSRR0) # SVSRR0
+ comb += e_out.write_fast3.ok.eq(1)
# RFID: needs to read SRR0/1
with m.If(do_out.insn_type == MicrOp.OP_RFID):
# TRAP read fast2 = SRR1
comb += e_out.read_fast2.data.eq(FastRegsEnum.SRR1) # SRR1
comb += e_out.read_fast2.ok.eq(1)
+ # TRAP read fast2 = SVSRR0
+ comb += e_out.read_fast3.data.eq(FastRegsEnum.SVSRR0) # SVSRR0
+ comb += e_out.read_fast3.ok.eq(1)
- # annoying simulator bug
- if hasattr(e_out, "asmcode") and hasattr(self.dec.op, "asmcode"):
- comb += e_out.asmcode.eq(self.dec.op.asmcode)
+ # annoying simulator bug.
+ # asmcode may end up getting used for perfcounters?
+ asmcode = self.op_get("asmcode")
+ if hasattr(e_out, "asmcode") and asmcode is not None:
+ comb += e_out.asmcode.eq(asmcode)
return m
- def trap(self, m, traptype, trapaddr, exc=None):
+ def trap(self, m, traptype, trapaddr, ldst_exc=None):
"""trap: this basically "rewrites" the decoded instruction as a trap
"""
comb = m.d.comb
- op, e = self.dec.op, self.e
+ e = self.e
comb += e.eq(0) # reset eeeeeverything
# start again
comb += self.do_copy("fn_unit", Function.TRAP, True)
comb += self.do_copy("trapaddr", trapaddr >> 4, True) # bottom 4 bits
comb += self.do_copy("traptype", traptype, True) # request type
- comb += self.do_copy("ldst_exc", exc, True) # request type
+ comb += self.do_copy("ldst_exc", ldst_exc, True) # request type
comb += self.do_copy("msr", self.state.msr, True) # copy of MSR "state"
comb += self.do_copy("cia", self.state.pc, True) # copy of PC "state"
+ comb += self.do_copy("svstate", self.state.svstate, True) # SVSTATE
regfile, regname, _ = cu.get_in_spec(idx)
rdflag, read = regspec_decode_read(e, regfile, regname)
rdl.append(rdflag)
- print("rdflags", rdl)
+ log("rdflags", rdl)
return Cat(*rdl)
projects / openpower-isa.git / blobdiff