move ffadds to not conflict with fptrans -- makes space for min/max/fmod/remainder ops

[openpower-isa.git] / src / openpower / decoder / power_decoder2.py

diff --git a/src/openpower/decoder/power_decoder2.py b/src/openpower/decoder/power_decoder2.py
index f804438ebeecfde38369a7be4e94091f61760d44..8cd7db702ba5be574173e704162f643317fefa05 100644 (file)
--- a/src/openpower/decoder/power_decoder2.py
+++ b/src/openpower/decoder/power_decoder2.py
@@ -1037,7 +1037,7 @@ class PowerDecodeSubset(Elaboratable):
                 '-----00101',  # ffmadds
                 '-----00110',  # ffnmsubs
                 '-----00111',  # ffnmadds
-                '1000001100',  # ffadds
+                '1111100000',  # ffadds
                 '-----11011',  # fdmadds
             ))
 
@@ -1272,12 +1272,14 @@ class PowerDecode2(PowerDecodeSubset):
 
             # get SVSTATE srcstep (TODO: elwidth etc.) needed below
             vl = Signal.like(self.state.svstate.vl)
+            maxvl = Signal.like(self.state.svstate.maxvl)
             subvl = Signal.like(self.rm_dec.rm_in.subvl)
             srcstep = Signal.like(self.state.svstate.srcstep)
             dststep = Signal.like(self.state.svstate.dststep)
             ssubstep = Signal.like(self.state.svstate.ssubstep)
             dsubstep = Signal.like(self.state.svstate.ssubstep)
             comb += vl.eq(self.state.svstate.vl)
+            comb += maxvl.eq(self.state.svstate.maxvl)
             comb += subvl.eq(self.rm_dec.rm_in.subvl)
             comb += srcstep.eq(self.state.svstate.srcstep)
             comb += dststep.eq(self.state.svstate.dststep)
@@ -1318,7 +1320,7 @@ class PowerDecode2(PowerDecodeSubset):
                     with m.If(dec_o2.reg_out.ok & dec_o2.fp_madd_en):
                         with m.If(~self.remap_active[i]):
                             with m.If(svdec.isvec):
-                                comb += offs.eq(vl)  # VL for Vectors
+                                comb += offs.eq(maxvl)  # MAXVL for Vectors
                 # detect if Vectorised: add srcstep/dststep if yes.
                 # to_reg is 7-bits, outs get dststep added, ins get srcstep
                 with m.If(svdec.isvec):