LdstLen, In1Sel, In2Sel, In3Sel,
OutSel, SPRfull, SPRreduced,
RCOE, SVP64LDSTmode, LDSTMode,
- SVEXTRA, SVEtype, SVPtype)
+ SVEXTRA, SVEType, SVPType)
from openpower.decoder.decode2execute1 import (Decode2ToExecute1Type, Data,
Decode2ToOperand)
comb += reg.data.eq(frs)
comb += reg.ok.eq(1)
+ # select Register FRT field,
+ frt = Signal(5, reset_less=True)
+ comb += frt.eq(self.dec.FRT)
+ with m.If(self.sel_in == In1Sel.FRT):
+ comb += reg.data.eq(frt)
+ comb += reg.ok.eq(1)
+
# decode Fast-SPR based on instruction type
with m.Switch(op.internal_op):
with m.Case(In2Sel.CONST_SH32): # unsigned - for shift
comb += self.imm_out.data.eq(self.dec.SH32)
comb += self.imm_out.ok.eq(1)
- with m.Case(In2Sel.CONST_XBI): # unsigned - for grevi
- comb += self.imm_out.data.eq(self.dec.FormXB.XBI)
- comb += self.imm_out.ok.eq(1)
return m
with m.Case(In3Sel.FRS):
comb += reg.data.eq(self.dec.FRS)
comb += reg.ok.eq(1)
+ with m.Case(In3Sel.FRA):
+ comb += reg.data.eq(self.dec.FRA)
+ comb += reg.ok.eq(1)
with m.Case(In3Sel.FRC):
comb += reg.data.eq(self.dec.FRC)
comb += reg.ok.eq(1)
with m.Case(OutSel.FRS):
comb += reg.data.eq(self.dec.FRS)
comb += reg.ok.eq(1)
+ with m.Case(OutSel.FRA):
+ comb += reg.data.eq(self.dec.FRA)
+ comb += reg.ok.eq(1)
with m.Case(OutSel.FRT):
comb += reg.data.eq(self.dec.FRT)
comb += reg.ok.eq(1)
sv_ptype = self.op_get("SV_Ptype")
sv_mode = self.op_get("SV_mode")
fn = self.op_get("function_unit")
- print ("sv_mode n", sv_mode)
comb += rm_dec.sv_mode.eq(sv_mode) # BRANCH/CROP/LDST_IMM etc.
comb += rm_dec.fn_in.eq(fn) # decode needs to know Fn type
comb += rm_dec.ptype_in.eq(sv_ptype) # Single/Twin predicated
with m.If((major == 4) & xo6.matches(
'111000', # pcdec
'110010', # maddedu
+ '111001', # maddedus
'111010', # divmod2du
'11010-', # dsld
'11011-', # dsrd
)):
comb += self.implicit_rs.eq(1)
comb += self.extend_rc_maxvl.eq(1) # RS=RT+MAXVL or RS=RC
+ # implicit RS for major 22, integer maddsubrs
+ with m.If((major == 22) & xo6.matches(
+ '-01000', # maddsubrs
+ '-01001', # maddrs
+ '-01011', # msubrs
+ )):
+ comb += self.implicit_rs.eq(1)
+ comb += self.extend_rb_maxvl.eq(1) # extend RB
# rc and oe out
comb += self.do_copy("rc", dec_rc.rc_out)
# should continue. this doesn't include predication bit-tests
loop = self.loop_continue
with m.Switch(self.op_get("SV_Ptype")):
- with m.Case(SVPtype.P2.value):
+ with m.Case(SVPType.P2.value):
# twin-predication
# TODO: *and cache-inhibited LD/ST!*
comb += loop.eq(~(self.no_in_vec | self.no_out_vec))
- with m.Case(SVPtype.P1.value):
+ with m.Case(SVPType.P1.value):
# single-predication, test relies on dest only
comb += loop.eq(~self.no_out_vec)
with m.Default():
(e.read_cr1, self.dec_cr_in, "cr_bitfield", crin_svdec, 0),
(e.read_cr2, self.dec_cr_in, "cr_bitfield_b", crin_svdec_b, 0),
(e.read_cr3, self.dec_cr_in, "cr_bitfield_o", crin_svdec_o, 0),
- (e.write_cr, self.dec_cr_out, "cr_bitfield", crout_svdec, 1)):
+ (e.write_cr, self.dec_cr_out, "cr_bitfield", crout_svdec, 1)):
fromreg = getattr(cr, name)
comb += svdec.extra.eq(extra) # EXTRA field of SVP64 RM
comb += svdec.etype.eq(sv_etype) # EXTRA2/3 for this insn