power_insn: remove the whitespaces properly

[openpower-isa.git] / src / openpower / decoder / power_enums.py

diff --git a/src/openpower/decoder/power_enums.py b/src/openpower/decoder/power_enums.py
index 3c8f9afdfd82d424ec510b2ed7e301c4e5c6bb6a..29faffb15031eb1d88294f6dabed9c0bbc7c3696 100644 (file)
--- a/src/openpower/decoder/power_enums.py
+++ b/src/openpower/decoder/power_enums.py
@@ -14,11 +14,16 @@ regfile size in HDL.  this is SPRreduced and the supported list is in
 get_spr_enum
 """
 
-from enum import Enum, unique
+from enum import (
+    auto,
+    Enum as _Enum,
+    unique,
+)
 import csv
 import os
 from os.path import dirname, join
 from collections import namedtuple
+import functools
 
 
 def find_wiki_dir():
@@ -63,6 +68,26 @@ def get_signal_name(name):
         name = "is_" + name
     return name.lower().replace(' ', '_')
 
+
+class Enum(_Enum):
+    @classmethod
+    def _missing_(cls, value):
+        if isinstance(value, str):
+            try:
+                if value == "":
+                    value = 0
+                else:
+                    value = int(value, 0)
+            except ValueError:
+                pass
+        keys = {item.name:item for item in cls}
+        values = {item.value:item for item in cls}
+        item = keys.get(value, values.get(value))
+        if item is None:
+            raise ValueError(value)
+        return item
+
+
 # this corresponds to which Function Unit (pipeline-with-Reservation-Stations)
 # is to process and guard the operation.  they are roughly divided by having
 # the same register input/output signature (X-Form, etc.)
@@ -86,6 +111,20 @@ class Function(Enum):
     VL = 1 << 13  # setvl
     FPU = 1 << 14  # FPU
 
+    @functools.lru_cache(maxsize=None)
+    def __repr__(self):
+        counter = 0
+        value = int(self.value)
+        if value != 0:
+            while value != 0:
+                counter += 1
+                value >>= 1
+            counter -= 1
+            desc = f"(1 << {counter})"
+        else:
+            desc = "0"
+        return f"<{self.__class__.__name__}.{self.name}: {desc}>"
+
 
 @unique
 class Form(Enum):
@@ -121,22 +160,38 @@ class Form(Enum):
     SVL = 29  # Simple-V for setvl instruction
     SVD = 30  # Simple-V for LD/ST bit-reverse, variant of D-Form
     SVDS = 31  # Simple-V for LD/ST bit-reverse, variant of DS-Form
-    SVM = 32  # Simple-V SHAPE mode - TEMPORARY TEMPORARY TEMPORARY
-    SVRM = 33  # Simple-V REMAP mode
-    TLI = 34  # ternlogi
-    XB = 35
-    BM2 = 36 # bmask
-    SVI = 37  # Simple-V Index Mode
+    SVM = 32  # Simple-V SHAPE mode
+    SVM2 = 33  # Simple-V SHAPE2 mode - fits into SVM
+    SVRM = 34  # Simple-V REMAP mode
+    TLI = 35  # ternlogi
+    XB = 36
+    BM2 = 37 # bmask
+    SVI = 38  # Simple-V Index Mode
+    VA2 = 39
+    SVC = 40
+    SVR = 41
 
 # Simple-V svp64 fields https://libre-soc.org/openpower/sv/svp64/
 
 
+class SVMode(Enum):
+    NORMAL = auto()
+    LDST_IDX = auto()
+    LDST_IMM = auto()
+    BRANCH = auto()
+    CROP = auto()
+
+
 @unique
 class SVPtype(Enum):
     NONE = 0
     P1 = 1
     P2 = 2
 
+    @classmethod
+    def _missing_(cls, value):
+        return {"1P": SVPtype.P1, "2P": SVPtype.P2}[value]
+
 
 @unique
 class SVEtype(Enum):
@@ -146,7 +201,7 @@ class SVEtype(Enum):
 
 
 @unique
-class SVEXTRA(Enum):
+class SVExtra(Enum):
     NONE = 0
     Idx0 = 1
     Idx1 = 2
@@ -154,6 +209,54 @@ class SVEXTRA(Enum):
     Idx3 = 4
     Idx_1_2 = 5  # due to weird BA/BB for crops
 
+# Backward compatibility
+SVEXTRA = SVExtra
+
+
+class SVExtraRegType(Enum):
+    NONE = None
+    SRC = 's'
+    DST = 'd'
+
+
+class SVExtraReg(Enum):
+    NONE = auto()
+    RA = auto()
+    RA_OR_ZERO = RA
+    RB = auto()
+    RC = auto()
+    RS = auto()
+    RT = auto()
+    RT_OR_ZERO = RT
+    FRA = auto()
+    FRB = auto()
+    FRC = auto()
+    FRS = auto()
+    FRT = auto()
+    CR = auto()
+    CR0 = auto()
+    CR1 = auto()
+    BF = auto()
+    BFA = auto()
+    BA = auto()
+    BB = auto()
+    BC = auto()
+    BI = auto()
+    BT = auto()
+    BFT = auto()
+    WHOLE_REG = auto()
+    SPR = auto()
+
+    @classmethod
+    def _missing_(cls, value):
+        selectors = (
+            In1Sel, In2Sel, In3Sel, CRInSel,
+            OutSel, CROutSel,
+        )
+        if isinstance(value, selectors):
+            return cls.__members__.get(value.name, cls.NONE)
+        return super()._missing_(value)
+
 
 @unique
 class SVP64PredMode(Enum):
@@ -253,7 +356,34 @@ class SVP64LDSTmode(Enum):
     INDEXED = 1
     ELSTRIDE = 2
     UNITSTRIDE = 3
-    SHIFT = 4
+
+
+class RegType(Enum):
+    GPR = 0
+    RA = GPR
+    RB = GPR
+    RC = GPR
+    RS = GPR
+    RT = GPR
+
+    FPR = 1
+    FRA = FPR
+    FRB = FPR
+    FRC = FPR
+    FRS = FPR
+    FRT = FPR
+
+    CR_REG = 2
+    BF = CR_REG
+    BFA = CR_REG
+
+    CR_BIT = 3
+    BA = CR_BIT
+    BB = CR_BIT
+    BC = CR_BIT
+    BI = CR_BIT
+    BT = CR_BIT
+    BFT = CR_BIT
 
 
 # supported instructions: make sure to keep up-to-date with CSV files
@@ -333,7 +463,8 @@ _insns = [
     "setvl",  # https://libre-soc.org/openpower/sv/setvl
     "svindex",  # https://libre-soc.org/openpower/sv/remap
     "svremap",  # https://libre-soc.org/openpower/sv/remap - TEMPORARY
-    "svshape",  # https://libre-soc.org/openpower/sv/remap
+    "svshape",  # https://libre-soc.org/openpower/sv/remap/#svshape
+    "svshape2",  # https://libre-soc.org/openpower/sv/remap/discussion TODO
     "svstep",  # https://libre-soc.org/openpower/sv/setvl
     "sim_cfg",
     "slbia", "sld", "slw", "srad", "sradi",
@@ -523,13 +654,16 @@ class OutSel(Enum):
 
 
 @unique
-class LdstLen(Enum):
+class LDSTLen(Enum):
     NONE = 0
     is1B = 1
     is2B = 2
     is4B = 4
     is8B = 8
 
+# Backward compatibility
+LdstLen = LDSTLen
+
 
 @unique
 class LDSTMode(Enum):
@@ -540,10 +674,11 @@ class LDSTMode(Enum):
 
 
 @unique
-class RC(Enum):
+class RCOE(Enum):
     NONE = 0
     ONE = 1
-    RC = 2
+    RC = 2    # includes OE
+    RC_ONLY = 3  # does not include OE
 
 
 @unique