power_insn: remove the whitespaces properly

[openpower-isa.git] / src / openpower / decoder / power_enums.py

diff --git a/src/openpower/decoder/power_enums.py b/src/openpower/decoder/power_enums.py
index 78015c362dea09d04358704034a7e4205260f0c1..29faffb15031eb1d88294f6dabed9c0bbc7c3696 100644 (file)
--- a/src/openpower/decoder/power_enums.py
+++ b/src/openpower/decoder/power_enums.py
@@ -15,6 +15,7 @@ get_spr_enum
 """
 
 from enum import (
+    auto,
     Enum as _Enum,
     unique,
 )
@@ -159,19 +160,28 @@ class Form(Enum):
     SVL = 29  # Simple-V for setvl instruction
     SVD = 30  # Simple-V for LD/ST bit-reverse, variant of D-Form
     SVDS = 31  # Simple-V for LD/ST bit-reverse, variant of DS-Form
-    SVM = 32  # Simple-V SHAPE mode - TEMPORARY TEMPORARY TEMPORARY
-    SVRM = 33  # Simple-V REMAP mode
-    TLI = 34  # ternlogi
-    XB = 35
-    BM2 = 36 # bmask
-    SVI = 37  # Simple-V Index Mode
-    VA2 = 38
-    SVC = 39
-    SVR = 40
+    SVM = 32  # Simple-V SHAPE mode
+    SVM2 = 33  # Simple-V SHAPE2 mode - fits into SVM
+    SVRM = 34  # Simple-V REMAP mode
+    TLI = 35  # ternlogi
+    XB = 36
+    BM2 = 37 # bmask
+    SVI = 38  # Simple-V Index Mode
+    VA2 = 39
+    SVC = 40
+    SVR = 41
 
 # Simple-V svp64 fields https://libre-soc.org/openpower/sv/svp64/
 
 
+class SVMode(Enum):
+    NORMAL = auto()
+    LDST_IDX = auto()
+    LDST_IMM = auto()
+    BRANCH = auto()
+    CROP = auto()
+
+
 @unique
 class SVPtype(Enum):
     NONE = 0
@@ -191,7 +201,7 @@ class SVEtype(Enum):
 
 
 @unique
-class SVEXTRA(Enum):
+class SVExtra(Enum):
     NONE = 0
     Idx0 = 1
     Idx1 = 2
@@ -199,6 +209,54 @@ class SVEXTRA(Enum):
     Idx3 = 4
     Idx_1_2 = 5  # due to weird BA/BB for crops
 
+# Backward compatibility
+SVEXTRA = SVExtra
+
+
+class SVExtraRegType(Enum):
+    NONE = None
+    SRC = 's'
+    DST = 'd'
+
+
+class SVExtraReg(Enum):
+    NONE = auto()
+    RA = auto()
+    RA_OR_ZERO = RA
+    RB = auto()
+    RC = auto()
+    RS = auto()
+    RT = auto()
+    RT_OR_ZERO = RT
+    FRA = auto()
+    FRB = auto()
+    FRC = auto()
+    FRS = auto()
+    FRT = auto()
+    CR = auto()
+    CR0 = auto()
+    CR1 = auto()
+    BF = auto()
+    BFA = auto()
+    BA = auto()
+    BB = auto()
+    BC = auto()
+    BI = auto()
+    BT = auto()
+    BFT = auto()
+    WHOLE_REG = auto()
+    SPR = auto()
+
+    @classmethod
+    def _missing_(cls, value):
+        selectors = (
+            In1Sel, In2Sel, In3Sel, CRInSel,
+            OutSel, CROutSel,
+        )
+        if isinstance(value, selectors):
+            return cls.__members__.get(value.name, cls.NONE)
+        return super()._missing_(value)
+
 
 @unique
 class SVP64PredMode(Enum):
@@ -405,7 +463,8 @@ _insns = [
     "setvl",  # https://libre-soc.org/openpower/sv/setvl
     "svindex",  # https://libre-soc.org/openpower/sv/remap
     "svremap",  # https://libre-soc.org/openpower/sv/remap - TEMPORARY
-    "svshape",  # https://libre-soc.org/openpower/sv/remap
+    "svshape",  # https://libre-soc.org/openpower/sv/remap/#svshape
+    "svshape2",  # https://libre-soc.org/openpower/sv/remap/discussion TODO
     "svstep",  # https://libre-soc.org/openpower/sv/setvl
     "sim_cfg",
     "slbia", "sld", "slw", "srad", "sradi",
@@ -615,10 +674,11 @@ class LDSTMode(Enum):
 
 
 @unique
-class RC(Enum):
+class RCOE(Enum):
     NONE = 0
     ONE = 1
-    RC = 2
+    RC = 2    # includes OE
+    RC_ONLY = 3  # does not include OE
 
 
 @unique