def _missing_(cls, value):
return {"1P": SVPtype.P1, "2P": SVPtype.P2}[value]
+ def __repr__(self):
+ return {
+ SVPtype.NONE: "NONE",
+ SVPtype.P1: "1P",
+ SVPtype.P2: "2P",
+ }[self]
+
@unique
class SVEtype(Enum):
EXTRA2 = 1
EXTRA3 = 2
+ def __repr__(self):
+ return self.name
+
+
+@unique
+class SVmask_src(Enum):
+ NO = 0
+ EN = 1
+
+ def __repr__(self):
+ return self.name
+
@unique
class SVExtra(Enum):
Idx3 = 4
Idx_1_2 = 5 # due to weird BA/BB for crops
+ def __repr__(self):
+ return {
+ SVExtra.NONE: "NONE",
+ SVExtra.Idx0: "[0]",
+ SVExtra.Idx1: "[1]",
+ SVExtra.Idx2: "[2]",
+ SVExtra.Idx3: "[3]",
+ SVExtra.Idx_1_2: "[1:2]",
+ }[self]
+
# Backward compatibility
SVEXTRA = SVExtra
@classmethod
def _missing_(cls, value):
selectors = (
- In1Sel, In2Sel, In3Sel, CRInSel,
+ In1Sel, In2Sel, In3Sel, CRInSel, CRIn2Sel,
OutSel, CROutSel,
)
if isinstance(value, selectors):
- return cls.__members__.get(value.name, cls.NONE)
+ return cls.__members__[value.name]
return super()._missing_(value)
SATURATE = 3
PREDRES = 4
BRANCH = 5
- PARALLEL = 6 # Parallel Reduction
@unique
FRS = FPR
FRT = FPR
- CR_REG = 2
+ CR_REG = 2 # actually CR Field. the CR register is 32-bit.
BF = CR_REG
BFA = CR_REG
- CR_BIT = 3
+ CR_BIT = 3 # refers to one bit of the 32-bit CR register
BA = CR_BIT
BB = CR_BIT
BC = CR_BIT
BI = CR_BIT
BT = CR_BIT
- BFT = CR_BIT
+
+ @classmethod
+ def _missing_(cls, value):
+ if isinstance(value, SVExtraReg):
+ return cls.__members__[value.name]
+ return super()._missing_(value)
+
+
+FPTRANS_INSNS = (
+ "fatan2", "fatan2s",
+ "fatan2pi", "fatan2pis",
+ "fpow", "fpows",
+ "fpown", "fpowns",
+ "fpowr", "fpowrs",
+ "frootn", "frootns",
+ "fhypot", "fhypots",
+ "frsqrt", "frsqrts",
+ "fcbrt", "fcbrts",
+ "frecip", "frecips",
+ "fexp2m1", "fexp2m1s",
+ "flog2p1", "flog2p1s",
+ "fexp2", "fexp2s",
+ "flog2", "flog2s",
+ "fexpm1", "fexpm1s",
+ "flogp1", "flogp1s",
+ "fexp", "fexps",
+ "flog", "flogs",
+ "fexp10m1", "fexp10m1s",
+ "flog10p1", "flog10p1s",
+ "fexp10", "fexp10s",
+ "flog10", "flog10s",
+ "fsin", "fsins",
+ "fcos", "fcoss",
+ "ftan", "ftans",
+ "fasin", "fasins",
+ "facos", "facoss",
+ "fatan", "fatans",
+ "fsinpi", "fsinpis",
+ "fcospi", "fcospis",
+ "ftanpi", "ftanpis",
+ "fasinpi", "fasinpis",
+ "facospi", "facospis",
+ "fatanpi", "fatanpis",
+ "fsinh", "fsinhs",
+ "fcosh", "fcoshs",
+ "ftanh", "ftanhs",
+ "fasinh", "fasinhs",
+ "facosh", "facoshs",
+ "fatanh", "fatanhs",
+ "fminnum08", "fminnum08s",
+ "fmaxnum08", "fmaxnum08s",
+ "fmin19", "fmin19s",
+ "fmax19", "fmax19s",
+ "fminnum19", "fminnum19s",
+ "fmaxnum19", "fmaxnum19s",
+ "fminc", "fmincs",
+ "fmaxc", "fmaxcs",
+ "fminmagnum08", "fminmagnum08s",
+ "fmaxmagnum08", "fmaxmagnum08s",
+ "fminmag19", "fminmag19s",
+ "fmaxmag19", "fmaxmag19s",
+ "fminmagnum19", "fminmagnum19s",
+ "fmaxmagnum19", "fmaxmagnum19s",
+ "fminmagc", "fminmagcs",
+ "fmaxmagc", "fmaxmagcs",
+ "fmod", "fmods",
+ "fremainder", "fremainders",
+)
# supported instructions: make sure to keep up-to-date with CSV files
"darn",
"dcbf", "dcbst", "dcbt", "dcbtst", "dcbz",
"divd", "divde", "divdeo", "divdeu",
- "divdeuo", "divdo", "divdu", "divduo", "divw", "divwe", "divweo",
+ "divdeuo", "divdo", "divdu", "divduo",
+ "divmod2du",
+ "divw", "divwe", "divweo",
"divweu", "divweuo", "divwo", "divwu", "divwuo",
+ "dsld", "dsrd",
"eieio", "eqv",
"extsb", "extsh", "extsw", "extswsli",
"fadd", "fadds", "fsub", "fsubs", # FP add / sub
"ffmsubs", "ffmadds", "ffnmsubs", "ffnmadds", # FFT FP 3-arg
"fmul", "fmuls", "fdiv", "fdivs", # FP mul / div
"fmr", "fabs", "fnabs", "fneg", "fcpsgn", # FP move/abs/neg
- "fsins", "fcoss", # FP SIN/COS
"fmvis", # FP load immediate
"fishmv", # Float Replace Lower-Half Single, Immediate
'grev', 'grev.', 'grevi', 'grevi.',
"lwz", "lwzcix", "lwzu", "lwzux", "lwzx", # more load word
# "lwabr", # load word SVP64 bit-reversed
# "lwzbr", "lwzubr", # more load word SVP64 bit-reversed
+ "maddedu",
"maddhd", "maddhdu", "maddld", # INT multiply-and-add
"mcrf", "mcrxr", "mcrxrx", "mfcr/mfocrf", # CR mvs
"mfmsr", "mfspr",
"nand", "neg", "nego",
"nop",
"nor", "or", "orc", "ori", "oris",
+ "pcdec",
"popcntb", "popcntd", "popcntw",
"prtyd", "prtyw",
"rfid",
"tw", "twi",
"wait",
"xor", "xori", "xoris",
+ *FPTRANS_INSNS,
]
# two-way lookup of instruction-to-index and vice-versa
OP_SVINDEX = 95
OP_FMVIS = 96
OP_FISHMV = 97
+ OP_PCDEC = 98
+ OP_MADDEDU = 99
+ OP_DIVMOD2DU = 100
+ OP_DSHL = 101
+ OP_DSHR = 102
@unique
RS = 4 # for some ALU/Logical operations
FRA = 5
FRS = 6
+ CIA = 7 # for addpcis
@unique
CONST_SVD = 15 # for SVD-Form
CONST_SVDS = 16 # for SVDS-Form
CONST_XBI = 17
+ CONST_DXHI4 = 18 # for addpcis
@unique
RT_OR_ZERO = 4
FRT = 5
FRS = 6
+ RS = 7
@unique
BC = 5
WHOLE_REG = 6
CR1 = 7
+ BA = 8
+
+
+@unique
+class CRIn2Sel(Enum):
+ NONE = 0
+ BB = 1
@unique