get_spr_enum
"""
-from enum import Enum, unique
+from enum import (
+ auto,
+ Enum as _Enum,
+ unique,
+)
import csv
import os
from os.path import dirname, join
from collections import namedtuple
+import functools
def find_wiki_dir():
name = "is_" + name
return name.lower().replace(' ', '_')
+
+class Enum(_Enum):
+ @classmethod
+ def _missing_(cls, value):
+ if isinstance(value, str):
+ try:
+ if value == "":
+ value = 0
+ else:
+ value = int(value, 0)
+ except ValueError:
+ pass
+ keys = {item.name:item for item in cls}
+ values = {item.value:item for item in cls}
+ item = keys.get(value, values.get(value))
+ if item is None:
+ raise ValueError(value)
+ return item
+
+
# this corresponds to which Function Unit (pipeline-with-Reservation-Stations)
# is to process and guard the operation. they are roughly divided by having
# the same register input/output signature (X-Form, etc.)
VL = 1 << 13 # setvl
FPU = 1 << 14 # FPU
+ @functools.lru_cache(maxsize=None)
+ def __repr__(self):
+ counter = 0
+ value = int(self.value)
+ if value != 0:
+ while value != 0:
+ counter += 1
+ value >>= 1
+ counter -= 1
+ desc = f"(1 << {counter})"
+ else:
+ desc = "0"
+ return f"<{self.__class__.__name__}.{self.name}: {desc}>"
+
@unique
class Form(Enum):
SVL = 29 # Simple-V for setvl instruction
SVD = 30 # Simple-V for LD/ST bit-reverse, variant of D-Form
SVDS = 31 # Simple-V for LD/ST bit-reverse, variant of DS-Form
- SVM = 32 # Simple-V SHAPE mode - TEMPORARY TEMPORARY TEMPORARY
- SVRM = 33 # Simple-V REMAP mode - TEMPORARY TEMPORARY TEMPORARY
- TLI = 34 # ternlogi
- XB = 35
- BM2 = 36 # bmask
+ SVM = 32 # Simple-V SHAPE mode
+ SVM2 = 33 # Simple-V SHAPE2 mode - fits into SVM
+ SVRM = 34 # Simple-V REMAP mode
+ TLI = 35 # ternlogi
+ XB = 36
+ BM2 = 37 # bmask
+ SVI = 38 # Simple-V Index Mode
+ VA2 = 39
+ SVC = 40
+ SVR = 41
# Simple-V svp64 fields https://libre-soc.org/openpower/sv/svp64/
+class SVMode(Enum):
+ NORMAL = auto()
+ LDST_IDX = auto()
+ LDST_IMM = auto()
+ BRANCH = auto()
+ CROP = auto()
+
+
@unique
class SVPtype(Enum):
NONE = 0
P1 = 1
P2 = 2
+ @classmethod
+ def _missing_(cls, value):
+ return {"1P": SVPtype.P1, "2P": SVPtype.P2}[value]
+
+ def __repr__(self):
+ return {
+ SVPtype.NONE: "NONE",
+ SVPtype.P1: "1P",
+ SVPtype.P2: "2P",
+ }[self]
+
@unique
class SVEtype(Enum):
EXTRA2 = 1
EXTRA3 = 2
+ def __repr__(self):
+ return self.name
+
@unique
-class SVEXTRA(Enum):
+class SVExtra(Enum):
NONE = 0
Idx0 = 1
Idx1 = 2
Idx3 = 4
Idx_1_2 = 5 # due to weird BA/BB for crops
+ def __repr__(self):
+ return {
+ SVExtra.NONE: "NONE",
+ SVExtra.Idx0: "[0]",
+ SVExtra.Idx1: "[1]",
+ SVExtra.Idx2: "[2]",
+ SVExtra.Idx3: "[3]",
+ SVExtra.Idx_1_2: "[1:2]",
+ }[self]
+
+# Backward compatibility
+SVEXTRA = SVExtra
+
+
+class SVExtraRegType(Enum):
+ NONE = None
+ SRC = 's'
+ DST = 'd'
+
+
+class SVExtraReg(Enum):
+ NONE = auto()
+ RA = auto()
+ RA_OR_ZERO = RA
+ RB = auto()
+ RC = auto()
+ RS = auto()
+ RT = auto()
+ RT_OR_ZERO = RT
+ FRA = auto()
+ FRB = auto()
+ FRC = auto()
+ FRS = auto()
+ FRT = auto()
+ CR = auto()
+ CR0 = auto()
+ CR1 = auto()
+ BF = auto()
+ BFA = auto()
+ BA = auto()
+ BB = auto()
+ BC = auto()
+ BI = auto()
+ BT = auto()
+ BFT = auto()
+ WHOLE_REG = auto()
+ SPR = auto()
+
+ @classmethod
+ def _missing_(cls, value):
+ selectors = (
+ In1Sel, In2Sel, In3Sel, CRInSel,
+ OutSel, CROutSel,
+ )
+ if isinstance(value, selectors):
+ return cls.__members__.get(value.name, cls.NONE)
+ return super()._missing_(value)
+
@unique
class SVP64PredMode(Enum):
INDEXED = 1
ELSTRIDE = 2
UNITSTRIDE = 3
- SHIFT = 4
+
+
+class RegType(Enum):
+ GPR = 0
+ RA = GPR
+ RB = GPR
+ RC = GPR
+ RS = GPR
+ RT = GPR
+
+ FPR = 1
+ FRA = FPR
+ FRB = FPR
+ FRC = FPR
+ FRS = FPR
+ FRT = FPR
+
+ CR_REG = 2 # actually CR Field. the CR register is 32-bit.
+ BF = CR_REG
+ BFA = CR_REG
+
+ CR_BIT = 3 # refers to one bit of the 32-bit CR register
+ BA = CR_BIT
+ BB = CR_BIT
+ BC = CR_BIT
+ BI = CR_BIT
+ BT = CR_BIT
+ BFT = CR_BIT
# supported instructions: make sure to keep up-to-date with CSV files
"fmul", "fmuls", "fdiv", "fdivs", # FP mul / div
"fmr", "fabs", "fnabs", "fneg", "fcpsgn", # FP move/abs/neg
"fsins", "fcoss", # FP SIN/COS
+ "fmvis", # FP load immediate
+ "fishmv", # Float Replace Lower-Half Single, Immediate
'grev', 'grev.', 'grevi', 'grevi.',
'grevw', 'grevw.', 'grevwi', 'grevwi.',
"hrfid", "icbi", "icbt", "isel", "isync",
"rlwimi", "rlwinm", "rlwnm",
"setb",
"setvl", # https://libre-soc.org/openpower/sv/setvl
+ "svindex", # https://libre-soc.org/openpower/sv/remap
"svremap", # https://libre-soc.org/openpower/sv/remap - TEMPORARY
- "svshape", # https://libre-soc.org/openpower/sv/remap
+ "svshape", # https://libre-soc.org/openpower/sv/remap/#svshape
+ "svshape2", # https://libre-soc.org/openpower/sv/remap/discussion TODO
"svstep", # https://libre-soc.org/openpower/sv/setvl
"sim_cfg",
"slbia", "sld", "slw", "srad", "sradi",
OP_ABSADD = 92
OP_CPROP = 93
OP_BMASK = 94
+ OP_SVINDEX = 95
+ OP_FMVIS = 96
+ OP_FISHMV = 97
@unique
@unique
-class LdstLen(Enum):
+class LDSTLen(Enum):
NONE = 0
is1B = 1
is2B = 2
is4B = 4
is8B = 8
+# Backward compatibility
+LdstLen = LDSTLen
+
@unique
class LDSTMode(Enum):
@unique
-class RC(Enum):
+class RCOE(Enum):
NONE = 0
ONE = 1
- RC = 2
+ RC = 2 # includes OE
+ RC_ONLY = 3 # does not include OE
@unique
projects / openpower-isa.git / blobdiff