class SVMode(Enum):
NORMAL = auto()
- LDST = auto()
+ LDST_IDX = auto()
+ LDST_IMM = auto()
BRANCH = auto()
CROP = auto()
def _missing_(cls, value):
return {"1P": SVPtype.P1, "2P": SVPtype.P2}[value]
+ def __repr__(self):
+ return {
+ SVPtype.NONE: "NONE",
+ SVPtype.P1: "1P",
+ SVPtype.P2: "2P",
+ }[self]
+
@unique
class SVEtype(Enum):
EXTRA2 = 1
EXTRA3 = 2
+ def __repr__(self):
+ return self.name
+
@unique
class SVExtra(Enum):
Idx3 = 4
Idx_1_2 = 5 # due to weird BA/BB for crops
+ def __repr__(self):
+ return {
+ SVExtra.NONE: "NONE",
+ SVExtra.Idx0: "[0]",
+ SVExtra.Idx1: "[1]",
+ SVExtra.Idx2: "[2]",
+ SVExtra.Idx3: "[3]",
+ SVExtra.Idx_1_2: "[1:2]",
+ }[self]
+
# Backward compatibility
SVEXTRA = SVExtra
FRS = FPR
FRT = FPR
- CR_REG = 2
+ CR_REG = 2 # actually CR Field. the CR register is 32-bit.
BF = CR_REG
BFA = CR_REG
- CR_BIT = 3
+ CR_BIT = 3 # refers to one bit of the 32-bit CR register
BA = CR_BIT
BB = CR_BIT
BC = CR_BIT
"setvl", # https://libre-soc.org/openpower/sv/setvl
"svindex", # https://libre-soc.org/openpower/sv/remap
"svremap", # https://libre-soc.org/openpower/sv/remap - TEMPORARY
- "svshape", # https://libre-soc.org/openpower/sv/remap
+ "svshape", # https://libre-soc.org/openpower/sv/remap/#svshape
+ "svshape2", # https://libre-soc.org/openpower/sv/remap/discussion TODO
"svstep", # https://libre-soc.org/openpower/sv/setvl
"sim_cfg",
"slbia", "sld", "slw", "srad", "sradi",