def get_csv(name):
+ retval = _get_csv(name)
+ return [i.copy() for i in retval]
+
+
+@functools.lru_cache()
+def _get_csv(name):
"""gets a not-entirely-csv-file-formatted database, which allows comments
"""
file_path = find_wiki_file(name)
SVM2 = 33 # Simple-V SHAPE2 mode - fits into SVM
SVRM = 34 # Simple-V REMAP mode
TLI = 35 # ternlogi
- XB = 36
+ # 36 available
BM2 = 37 # bmask
SVI = 38 # Simple-V Index Mode
VA2 = 39
NONE = 0
P1 = 1
P2 = 2
+ P2M = 3 # for mixed EXTRA3/3/2 where MASK_SRC is RM[6,7,18]
@classmethod
def _missing_(cls, desc):
- return {"1P": SVPType.P1, "2P": SVPType.P2}.get(desc)
+ return {"1P": SVPType.P1, "2P": SVPType.P2, "2PM": SVPType.P2M}.get(desc)
- def __repr__(self):
+ def __str__(self):
return {
SVPType.NONE: "NONE",
SVPType.P1: "1P",
SVPType.P2: "2P",
+ SVPType.P2M: "2PM",
}[self]
@unique
class SVEType(Enum):
+ """SVEType
+ * EXTRA2 : 0: [10,11] 1: [12,13] 2: [14,15] 3: [16,17] unused: [18]
+ * EXTRA3 : 0: [10,11,12] 1: [13,14,15] mask: [16,17,18]
+ * EXTRA32: 0: [10,11,12] 1: [13,14,15] 2: [16,17] mask: [6,7,18]
+ """
NONE = 0
EXTRA2 = 1
EXTRA3 = 2
+ EXTRA32 = 3 # mixed EXTRA3 and EXTRA2 using RM bits 6&7 for MASK_SRC
- def __repr__(self):
+ def __str__(self):
return self.name
NO = 0
EN = 1
- def __repr__(self):
+ def __str__(self):
return self.name
Idx3 = 4
Idx_1_2 = 5 # due to weird BA/BB for crops
- def __repr__(self):
+ def __str__(self):
return {
SVExtra.NONE: "NONE",
- SVExtra.Idx0: "[0]",
- SVExtra.Idx1: "[1]",
- SVExtra.Idx2: "[2]",
- SVExtra.Idx3: "[3]",
- SVExtra.Idx_1_2: "[1:2]",
+ SVExtra.Idx0: "EXTRA0",
+ SVExtra.Idx1: "EXTRA1",
+ SVExtra.Idx2: "EXTRA2",
+ SVExtra.Idx3: "EXTRA3",
+ SVExtra.Idx_1_2: "EXTRA1/EXTRA2",
}[self]
# Backward compatibility
SVEXTRA = SVExtra
-class SVExtraRegType(Enum):
- NONE = None
- SRC = 's'
- DST = 'd'
-
-
-class SVExtraReg(Enum):
+class Reg(Enum):
NONE = auto()
RA = auto()
- RA_OR_ZERO = RA
+ RA_OR_ZERO = auto()
RB = auto()
RC = auto()
RS = auto()
RT = auto()
- RT_OR_ZERO = RT
+ RT_OR_ZERO = auto()
FRA = auto()
FRB = auto()
FRC = auto()
FRSp = auto()
FRTp = auto()
+ def __str__(self):
+ return self.name
+
@classmethod
def _missing_(cls, desc):
selectors = (
return cls.__members__.get(desc)
+ @property
+ def alias(self):
+ alias = {
+ Reg.RSp: Reg.RS,
+ Reg.RTp: Reg.RT,
+ Reg.FRAp: Reg.FRA,
+ Reg.FRBp: Reg.FRB,
+ Reg.FRSp: Reg.FRS,
+ Reg.FRTp: Reg.FRT,
+ }.get(self)
+ if alias is not None:
+ return alias
+
+ alias = {
+ Reg.RA_OR_ZERO: Reg.RA,
+ Reg.RT_OR_ZERO: Reg.RT,
+ }.get(self)
+ if alias is not None:
+ return alias
+
+ return self
+
+ @property
+ def or_zero(self):
+ return (self in (
+ Reg.RA_OR_ZERO,
+ Reg.RT_OR_ZERO,
+ ))
+
+ @property
+ def pair(self):
+ return (self in (
+ Reg.RSp,
+ Reg.RTp,
+ Reg.FRAp,
+ Reg.FRBp,
+ Reg.FRSp,
+ Reg.FRTp,
+ ))
+
@unique
class SVP64PredMode(Enum):
@classmethod
def _missing_(cls, value):
- if isinstance(value, SVExtraReg):
+ if isinstance(value, Reg):
return cls.__members__.get(value.name)
return super()._missing_(value)
"fasinh", "fasinhs",
"facosh", "facoshs",
"fatanh", "fatanhs",
- # fmin*/fmax* need to be replaced with fminmax
- # https://bugs.libre-soc.org/show_bug.cgi?id=1057
- # commented for now to make space for fmv/cvt
- # "fminnum08", "fminnum08s",
- # "fmaxnum08", "fmaxnum08s",
- # "fmin19", "fmin19s",
- # "fmax19", "fmax19s",
- # "fminnum19", "fminnum19s",
- # "fmaxnum19", "fmaxnum19s",
- # "fminc", "fmincs",
- # "fmaxc", "fmaxcs",
- # "fminmagnum08", "fminmagnum08s",
- # "fmaxmagnum08", "fmaxmagnum08s",
- # "fminmag19", "fminmag19s",
- # "fmaxmag19", "fmaxmag19s",
- # "fminmagnum19", "fminmagnum19s",
- # "fmaxmagnum19", "fmaxmagnum19s",
- # "fminmagc", "fminmagcs",
- # "fmaxmagc", "fmaxmagcs",
+ "fminmax",
"fmod", "fmods",
"fremainder", "fremainders",
)
"absdacs", "absdacu", # AV bitmanip
"avgadd", # AV bitmanip
"b", "bc", "bcctr", "bclr", "bctar",
+ "brh", "brw", "brd",
"bmask", # AV bitmanip
"bpermd",
"cbcdtd",
"cdtbcd",
+ "cfuged",
"cmp", "cmpb", "cmpeqb", "cmpi", "cmpl", "cmpli", "cmprb",
- "cntlzd", "cntlzw", "cnttzd", "cnttzw",
+ "cntlzd", "cntlzdm", "cntlzw", "cnttzd", "cnttzdm", "cnttzw",
"cprop", # AV bitmanip
"crand", "crandc", "creqv",
"crnand", "crnor", "cror", "crorc", "crxor",
"fmr", "fabs", "fnabs", "fneg", "fcpsgn", # FP move/abs/neg
"fmvis", # FP load immediate
"fishmv", # Float Replace Lower-Half Single, Immediate
- "fcvttg", "fcvttgo", "fcvttgs", "fcvttgso",
- "fmvtg", "fmvtgs",
- "fcvtfg", "fcvtfgs",
- "fmvfg", "fmvfgs",
- 'grev', 'grev.', 'grevi', 'grevi.',
- 'grevw', 'grevw.', 'grevwi', 'grevwi.',
+ "cffpr", "cffpro",
+ "mffpr", "mffprs",
+ "ctfpr", "ctfprs",
+ "mtfpr", "mtfprs",
"hrfid", "icbi", "icbt", "isel", "isync",
"lbarx", "lbz", "lbzcix", "lbzu", "lbzux", "lbzx", # load byte
"ld", "ldarx", "ldbrx", "ldu", "ldux", "ldx", # load double
"maddhd", "maddhdu", "maddld", # INT multiply-and-add
"maddsubrs", # Integer DCT Butterfly Add Sub and Round Shift
"maddrs", # Integer DCT Butterfly Add and Accumulate and Round Shift
+ "msubrs", # Integer DCT Butterfly Subtract from and Round Shift
"mcrf", "mcrxr", "mcrxrx", "mfcr/mfocrf", # CR mvs
"mfmsr", "mfspr",
"minmax", # AV bitmanip
"nop",
"nor", "or", "orc", "ori", "oris",
"pcdec",
+ "pdepd", "pextd",
"popcntb", "popcntd", "popcntw",
"prtyd", "prtyw",
"rfid",
"rldcl", "rldcr", "rldic", "rldicl", "rldicr", "rldimi",
"rlwimi", "rlwinm", "rlwnm",
"setb",
+ "setbc", "setbcr", "setnbc", "setnbcr",
"setvl", # https://libre-soc.org/openpower/sv/setvl
"svindex", # https://libre-soc.org/openpower/sv/remap
"svremap", # https://libre-soc.org/openpower/sv/remap - TEMPORARY
"svshape2", # https://libre-soc.org/openpower/sv/remap/discussion TODO
"svstep", # https://libre-soc.org/openpower/sv/setvl
"sim_cfg",
- "shadd", "shaddw", "shadduw",
+ "sadd", "saddw", "sadduw",
"slbia", "sld", "slw", "srad", "sradi",
"sraw", "srawi", "srd", "srw",
"stb", "stbcix", "stbcx", "stbu", "stbux", "stbx",
OP_CBCDTD = 85
OP_TERNLOG = 86
OP_FETCH_FAILED = 87
- OP_GREV = 88
+ # 88 available
OP_MINMAX = 89
OP_AVGADD = 90
OP_ABSDIFF = 91
OP_SHADD = 103
OP_MADDSUBRS = 104
OP_MADDRS = 105
+ OP_MSUBRS = 106
+ OP_BYTEREV = 107
+ OP_CFUGE = 108
+ OP_PDEP = 109
+ OP_PEXT = 110
+ OP_SETBC = 111
+
+
+class SelType(Enum):
+ NONE = None
+ SRC = 's'
+ DST = 'd'
+
+ def __str__(self):
+ return {
+ SelType.NONE: "NONE",
+ SelType.SRC: "SRC",
+ SelType.DST: "DST",
+ }[self]
class In1Sel(Enum):
CIA = 8 # for addpcis
RT = 9
+ def __str__(self):
+ if self is In1Sel.RA_OR_ZERO:
+ return "RA0"
+ return self.name
+
+ @property
+ def type(self):
+ if self is In1Sel.NONE:
+ return SelType.NONE
+ return SelType.SRC
+
class In2Sel(Enum):
NONE = 0
FRBp = FRB
CONST_SVD = 15 # for SVD-Form
CONST_SVDS = 16 # for SVDS-Form
- CONST_XBI = 17
+ # 17 available
CONST_DXHI4 = 18 # for addpcis
CONST_DQ = 19 # for ld/st-quad
+ def __str__(self):
+ return self.name
+
+ @property
+ def type(self):
+ if self is In2Sel.NONE:
+ return SelType.NONE
+ return SelType.SRC
+
class In3Sel(Enum):
NONE = 0
RTp = RT
FRA = 7
+ def __str__(self):
+ return self.name
+
+ @property
+ def type(self):
+ if self is In3Sel.NONE:
+ return SelType.NONE
+ return SelType.SRC
+
class OutSel(Enum):
NONE = 0
RSp = RS
FRA = 8
+ def __str__(self):
+ if self is OutSel.RT_OR_ZERO:
+ return "RT0"
+ return self.name
+
+ @property
+ def type(self):
+ if self is OutSel.NONE:
+ return SelType.NONE
+ return SelType.DST
+
@unique
class LDSTLen(Enum):
CR1 = 7
BA = 8
+ def __str__(self):
+ return self.name
+
+ @property
+ def type(self):
+ if self is CRInSel.NONE:
+ return SelType.NONE
+ return SelType.SRC
+
@unique
class CRIn2Sel(Enum):
NONE = 0
BB = 1
+ def __str__(self):
+ return self.name
+
+ @property
+ def type(self):
+ if self is CRIn2Sel.NONE:
+ return SelType.NONE
+ return SelType.SRC
+
@unique
class CROutSel(Enum):
WHOLE_REG = 4
CR1 = 5
+ def __str__(self):
+ return self.name
+
+ @property
+ def type(self):
+ if self is CROutSel.NONE:
+ return SelType.NONE
+ return SelType.DST
+
# SPRs - Special-Purpose Registers. See V3.0B Figure 18 p971 and
# http://libre-riscv.org/openpower/isatables/sprs.csv
'inc_flag',
)
+
+@unique
+class FMinMaxMode(Enum):
+ """ FMM field for fminmax instruction.
+ enumerant names match assembly aliases.
+ """
+ fminnum08 = 0b0000
+ fmin19 = 0b0001
+ fminnum19 = 0b0010
+ fminc = 0b0011
+ fminmagnum08 = 0b0100
+ fminmag19 = 0b0101
+ fminmagnum19 = 0b0110
+ fminmagc = 0b0111
+ fmaxnum08 = 0b1000
+ fmax19 = 0b1001
+ fmaxnum19 = 0b1010
+ fmaxc = 0b1011
+ fmaxmagnum08 = 0b1100
+ fmaxmag19 = 0b1101
+ fmaxmagnum19 = 0b1110
+ fmaxmagc = 0b1111
+
if __name__ == '__main__':
# find out what the heck is in SPR enum :)
print("sprs full", len(SPRfull))
projects / openpower-isa.git / blobdiff