SVC = 40
SVR = 41
CRB = 42 # crternlogi / crbinlut
+ MM = 43 # [f]minmax[s][.]
+ CW = 44
+ CW2 = 45
+ DCT = 46 # fdmadds
# Simple-V svp64 fields https://libre-soc.org/openpower/sv/svp64/
NONE = 0
P1 = 1
P2 = 2
+ P2M = 3 # for mixed EXTRA3/3/2 where MASK_SRC is RM[6,7,18]
@classmethod
def _missing_(cls, desc):
- return {"1P": SVPType.P1, "2P": SVPType.P2}.get(desc)
+ return {"1P": SVPType.P1, "2P": SVPType.P2, "2PM": SVPType.P2M}.get(desc)
def __repr__(self):
return {
SVPType.NONE: "NONE",
SVPType.P1: "1P",
SVPType.P2: "2P",
+ SVPType.P2M: "2PM",
}[self]
@unique
class SVEType(Enum):
+ """SVEType
+ * EXTRA2 : 0: [10,11] 1: [12,13] 2: [14,15] 3: [16,17] unused: [18]
+ * EXTRA3 : 0: [10,11,12] 1: [13,14,15] mask: [16,17,18]
+ * EXTRA32: 0: [10,11,12] 1: [13,14,15] 2: [16,17] mask: [6,7,18]
+ """
NONE = 0
EXTRA2 = 1
EXTRA3 = 2
+ EXTRA32 = 3 # mixed EXTRA3 and EXTRA2 using RM bits 6&7 for MASK_SRC
def __repr__(self):
return self.name
def __repr__(self):
return {
- SVExtra.NONE: "NONE",
- SVExtra.Idx0: "[0]",
- SVExtra.Idx1: "[1]",
- SVExtra.Idx2: "[2]",
- SVExtra.Idx3: "[3]",
- SVExtra.Idx_1_2: "[1:2]",
+ SVExtra.NONE: "none",
+ SVExtra.Idx0: "extra0",
+ SVExtra.Idx1: "extra1",
+ SVExtra.Idx2: "extra2",
+ SVExtra.Idx3: "extra3",
+ SVExtra.Idx_1_2: "extra1/extra2",
}[self]
# Backward compatibility
SVEXTRA = SVExtra
-class SVExtraRegType(Enum):
- NONE = None
- SRC = 's'
- DST = 'd'
-
-
class SVExtraReg(Enum):
NONE = auto()
RA = auto()
return cls.__members__.get(desc)
+ @property
+ def alias(self):
+ alias = {
+ SVExtraReg.RSp: SVExtraReg.RS,
+ SVExtraReg.RTp: SVExtraReg.RT,
+ SVExtraReg.FRAp: SVExtraReg.FRA,
+ SVExtraReg.FRBp: SVExtraReg.FRB,
+ SVExtraReg.FRSp: SVExtraReg.FRS,
+ SVExtraReg.FRTp: SVExtraReg.FRT,
+ }.get(self)
+ if alias is not None:
+ return alias
+
+ alias = {
+ SVExtraReg.RA_OR_ZERO: SVExtraReg.RA,
+ SVExtraReg.RT_OR_ZERO: SVExtraReg.RT,
+ }.get(self)
+ if alias is not None:
+ return alias
+
+ return self
+
@unique
class SVP64PredMode(Enum):
MAPREDUCE = 1
FFIRST = 2
SATURATE = 3
- PREDRES = 4
BRANCH = 5
"fasinh", "fasinhs",
"facosh", "facoshs",
"fatanh", "fatanhs",
- "fminnum08", "fminnum08s",
- "fmaxnum08", "fmaxnum08s",
- "fmin19", "fmin19s",
- "fmax19", "fmax19s",
- "fminnum19", "fminnum19s",
- "fmaxnum19", "fmaxnum19s",
- "fminc", "fmincs",
- "fmaxc", "fmaxcs",
- "fminmagnum08", "fminmagnum08s",
- "fmaxmagnum08", "fmaxmagnum08s",
- "fminmag19", "fminmag19s",
- "fmaxmag19", "fmaxmag19s",
- "fminmagnum19", "fminmagnum19s",
- "fmaxmagnum19", "fmaxmagnum19s",
- "fminmagc", "fminmagcs",
- "fmaxmagc", "fmaxmagcs",
+ # fmin*/fmax* need to be replaced with fminmax
+ # https://bugs.libre-soc.org/show_bug.cgi?id=1057
+ # commented for now to make space for fmv/cvt
+ # "fminnum08", "fminnum08s",
+ # "fmaxnum08", "fmaxnum08s",
+ # "fmin19", "fmin19s",
+ # "fmax19", "fmax19s",
+ # "fminnum19", "fminnum19s",
+ # "fmaxnum19", "fmaxnum19s",
+ # "fminc", "fmincs",
+ # "fmaxc", "fmaxcs",
+ # "fminmagnum08", "fminmagnum08s",
+ # "fmaxmagnum08", "fmaxmagnum08s",
+ # "fminmag19", "fminmag19s",
+ # "fmaxmag19", "fmaxmag19s",
+ # "fminmagnum19", "fminmagnum19s",
+ # "fmaxmagnum19", "fmaxmagnum19s",
+ # "fminmagc", "fminmagcs",
+ # "fmaxmagc", "fmaxmagcs",
"fmod", "fmods",
"fremainder", "fremainders",
)
"NONE", "add", "addc", "addco", "adde", "addeo",
"addi", "addic", "addic.", "addis",
"addme", "addmeo", "addo", "addze", "addzeo",
+ "addex",
"addg6s",
"and", "andc", "andi.", "andis.",
"attn",
"fmr", "fabs", "fnabs", "fneg", "fcpsgn", # FP move/abs/neg
"fmvis", # FP load immediate
"fishmv", # Float Replace Lower-Half Single, Immediate
+ "fcvttg", "fcvttgo", "fcvttgs", "fcvttgso",
+ "fmvtg", "fmvtgs",
+ "fcvtfg", "fcvtfgs",
+ "fmvfg", "fmvfgs",
'grev', 'grev.', 'grevi', 'grevi.',
'grevw', 'grevw.', 'grevwi', 'grevwi.',
"hrfid", "icbi", "icbt", "isel", "isync",
# "lwzbr", "lwzubr", # more load word SVP64 bit-reversed
"maddedu", "maddedus",
"maddhd", "maddhdu", "maddld", # INT multiply-and-add
+ "maddsubrs", # Integer DCT Butterfly Add Sub and Round Shift
+ "maddrs", # Integer DCT Butterfly Add and Accumulate and Round Shift
"mcrf", "mcrxr", "mcrxrx", "mfcr/mfocrf", # CR mvs
"mfmsr", "mfspr",
- "mins", "maxs", "minu", "maxu", # AV bitmanip
+ "minmax", # AV bitmanip
"modsd", "modsw", "modud", "moduw",
"mtcrf/mtocrf", "mtmsr", "mtmsrd", "mtspr",
"mulhd", "mulhdu", "mulhw", "mulhwu", "mulld", "mulldo",
"svshape2", # https://libre-soc.org/openpower/sv/remap/discussion TODO
"svstep", # https://libre-soc.org/openpower/sv/setvl
"sim_cfg",
- "shadd", "shadduw",
+ "sadd", "saddw", "sadduw",
"slbia", "sld", "slw", "srad", "sradi",
"sraw", "srawi", "srd", "srw",
"stb", "stbcix", "stbcx", "stbu", "stbux", "stbx",
OP_DSHL = 101
OP_DSHR = 102
OP_SHADD = 103
+ OP_MADDSUBRS = 104
+ OP_MADDRS = 105
+
+
+class SelType(Enum):
+ NONE = None
+ SRC = 's'
+ DST = 'd'
+
+ def __repr__(self):
+ return {
+ SelType.NONE: "none",
+ SelType.SRC: "src",
+ SelType.DST: "dst",
+ }[self]
class In1Sel(Enum):
FRAp = FRA
FRS = 6
FRSp = FRS
- CIA = 7 # for addpcis
+ FRT = 7
+ CIA = 8 # for addpcis
+ RT = 9
+
+ @property
+ def type(self):
+ if self is In1Sel.NONE:
+ return SelType.NONE
+ return SelType.SRC
class In2Sel(Enum):
CONST_DXHI4 = 18 # for addpcis
CONST_DQ = 19 # for ld/st-quad
+ @property
+ def type(self):
+ if self is In2Sel.NONE:
+ return SelType.NONE
+ return SelType.SRC
+
class In3Sel(Enum):
NONE = 0
RC = 5 # for SVP64 bit-reverse LD/ST
RT = 6 # for ternlog[i]
RTp = RT
+ FRA = 7
+
+ @property
+ def type(self):
+ if self is In3Sel.NONE:
+ return SelType.NONE
+ return SelType.SRC
class OutSel(Enum):
FRSp = FRS
RS = 7
RSp = RS
+ FRA = 8
+
+ @property
+ def type(self):
+ if self is OutSel.NONE:
+ return SelType.NONE
+ return SelType.DST
@unique
CR1 = 7
BA = 8
+ @property
+ def type(self):
+ if self is CRInSel.NONE:
+ return SelType.NONE
+ return SelType.SRC
+
@unique
class CRIn2Sel(Enum):
NONE = 0
BB = 1
+ @property
+ def type(self):
+ if self is CRIn2Sel.NONE:
+ return SelType.NONE
+ return SelType.SRC
+
@unique
class CROutSel(Enum):
WHOLE_REG = 4
CR1 = 5
+ @property
+ def type(self):
+ if self is CROutSel.NONE:
+ return SelType.NONE
+ return SelType.DST
+
# SPRs - Special-Purpose Registers. See V3.0B Figure 18 p971 and
# http://libre-riscv.org/openpower/isatables/sprs.csv
MSRSpec = namedtuple("MSRSpec", ["dr", "pr", "sf"])
+# flags for bfp_* functions
+BFP_FLAG_NAMES = (
+ 'vxsnan_flag',
+ 'vximz_flag',
+ 'vxidi_flag',
+ 'vxisi_flag',
+ 'vxzdz_flag',
+ 'vxsqrt_flag',
+ 'vxcvi_flag',
+ 'vxvc_flag',
+ 'ox_flag',
+ 'ux_flag',
+ 'xx_flag',
+ 'zx_flag',
+ 'inc_flag',
+)
+
if __name__ == '__main__':
# find out what the heck is in SPR enum :)
print("sprs full", len(SPRfull))
projects / openpower-isa.git / blobdiff