-# SPDX-License: LGPLv3+
+# SPDX-License-Identifier: LGPL-3-or-later
# Copyright (C) 2020, 2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
# Copyright (C) 2020, Michael Nolan
get_spr_enum
"""
-from enum import Enum, unique
+from enum import (
+ Enum as _Enum,
+ unique,
+)
import csv
import os
from os.path import dirname, join
from collections import namedtuple
+import functools
def find_wiki_dir():
def get_csv(name):
+ """gets a not-entirely-csv-file-formatted database, which allows comments
+ """
file_path = find_wiki_file(name)
with open(file_path, 'r') as csvfile:
+ csvfile = filter(lambda row: row[0] !='#', csvfile) # strip "#..."
reader = csv.DictReader(csvfile)
return list(reader)
name = "is_" + name
return name.lower().replace(' ', '_')
+
+class Enum(_Enum):
+ @classmethod
+ def _missing_(cls, value):
+ if isinstance(value, str):
+ try:
+ if value == "":
+ value = 0
+ else:
+ value = int(value, 0)
+ except ValueError:
+ pass
+ keys = {item.name:item for item in cls}
+ values = {item.value:item for item in cls}
+ item = keys.get(value, values.get(value))
+ if item is None:
+ raise ValueError(value)
+ return item
+
+
# this corresponds to which Function Unit (pipeline-with-Reservation-Stations)
# is to process and guard the operation. they are roughly divided by having
# the same register input/output signature (X-Form, etc.)
VL = 1 << 13 # setvl
FPU = 1 << 14 # FPU
+ @functools.lru_cache(maxsize=None)
+ def __repr__(self):
+ counter = 0
+ value = int(self.value)
+ if value != 0:
+ while value != 0:
+ counter += 1
+ value >>= 1
+ counter -= 1
+ desc = f"(1 << {counter})"
+ else:
+ desc = "0"
+ return f"<{self.__class__.__name__}.{self.name}: {desc}>"
+
@unique
class Form(Enum):
SVD = 30 # Simple-V for LD/ST bit-reverse, variant of D-Form
SVDS = 31 # Simple-V for LD/ST bit-reverse, variant of DS-Form
SVM = 32 # Simple-V SHAPE mode - TEMPORARY TEMPORARY TEMPORARY
- SVRM = 33 # Simple-V REMAP mode - TEMPORARY TEMPORARY TEMPORARY
+ SVRM = 33 # Simple-V REMAP mode
TLI = 34 # ternlogi
+ XB = 35
+ BM2 = 36 # bmask
+ SVI = 37 # Simple-V Index Mode
+ VA2 = 38
+ SVC = 39
+ SVR = 40
# Simple-V svp64 fields https://libre-soc.org/openpower/sv/svp64/
P1 = 1
P2 = 2
+ @classmethod
+ def _missing_(cls, value):
+ return {"1P": SVPtype.P1, "2P": SVPtype.P2}[value]
+
@unique
class SVEtype(Enum):
INDEXED = 1
ELSTRIDE = 2
UNITSTRIDE = 3
- SHIFT = 4
+
+
+class RegType(Enum):
+ GPR = 0
+ RA = GPR
+ RB = GPR
+ RC = GPR
+ RS = GPR
+ RT = GPR
+
+ FPR = 1
+ FRA = FPR
+ FRB = FPR
+ FRC = FPR
+ FRS = FPR
+ FRT = FPR
+
+ CR_REG = 2
+ BF = CR_REG
+ BFA = CR_REG
+
+ CR_BIT = 3
+ BA = CR_BIT
+ BB = CR_BIT
+ BC = CR_BIT
+ BI = CR_BIT
+ BT = CR_BIT
+ BFT = CR_BIT
# supported instructions: make sure to keep up-to-date with CSV files
"addg6s",
"and", "andc", "andi.", "andis.",
"attn",
+ "absdu", "absds", # AV bitmanip
+ "absdacs", "absdacu", # AV bitmanip
+ "avgadd", # AV bitmanip
"b", "bc", "bcctr", "bclr", "bctar",
+ "bmask", # AV bitmanip
"bpermd",
"cbcdtd",
"cdtbcd",
"cmp", "cmpb", "cmpeqb", "cmpi", "cmpl", "cmpli", "cmprb",
"cntlzd", "cntlzw", "cnttzd", "cnttzw",
+ "cprop", # AV bitmanip
"crand", "crandc", "creqv",
"crnand", "crnor", "cror", "crorc", "crxor",
"darn",
"divd", "divde", "divdeo", "divdeu",
"divdeuo", "divdo", "divdu", "divduo", "divw", "divwe", "divweo",
"divweu", "divweuo", "divwo", "divwu", "divwuo",
- "eqv",
+ "eieio", "eqv",
"extsb", "extsh", "extsw", "extswsli",
"fadd", "fadds", "fsub", "fsubs", # FP add / sub
"fcfids", "fcfidus", "fsqrts", "fres", "frsqrtes", # FP stuff
"fmul", "fmuls", "fdiv", "fdivs", # FP mul / div
"fmr", "fabs", "fnabs", "fneg", "fcpsgn", # FP move/abs/neg
"fsins", "fcoss", # FP SIN/COS
+ "fmvis", # FP load immediate
+ "fishmv", # Float Replace Lower-Half Single, Immediate
+ 'grev', 'grev.', 'grevi', 'grevi.',
+ 'grevw', 'grevw.', 'grevwi', 'grevwi.',
"hrfid", "icbi", "icbt", "isel", "isync",
- "lbarx", "lbz", "lbzu", "lbzux", "lbzx", # load byte
+ "lbarx", "lbz", "lbzcix", "lbzu", "lbzux", "lbzx", # load byte
"ld", "ldarx", "ldbrx", "ldu", "ldux", "ldx", # load double
# "lbzbr", "lbzubr", # load byte SVP64 bit-reversed
# "ldbr", "ldubr", # load double SVP64 bit-reversed
"maddhd", "maddhdu", "maddld", # INT multiply-and-add
"mcrf", "mcrxr", "mcrxrx", "mfcr/mfocrf", # CR mvs
"mfmsr", "mfspr",
+ "mins", "maxs", "minu", "maxu", # AV bitmanip
"modsd", "modsw", "modud", "moduw",
"mtcrf/mtocrf", "mtmsr", "mtmsrd", "mtspr",
"mulhd", "mulhdu", "mulhw", "mulhwu", "mulld", "mulldo",
"rlwimi", "rlwinm", "rlwnm",
"setb",
"setvl", # https://libre-soc.org/openpower/sv/setvl
+ "svindex", # https://libre-soc.org/openpower/sv/remap
"svremap", # https://libre-soc.org/openpower/sv/remap - TEMPORARY
"svshape", # https://libre-soc.org/openpower/sv/remap
"svstep", # https://libre-soc.org/openpower/sv/setvl
"sync",
"ternlogi",
"td", "tdi",
- "tlbie", "tlbiel",
+ "tlbie", "tlbiel", "tlbsync",
"tw", "twi",
+ "wait",
"xor", "xori", "xoris",
]
OP_CDTBCD = 84
OP_CBCDTD = 85
OP_TERNLOG = 86
+ OP_FETCH_FAILED = 87
+ OP_GREV = 88
+ OP_MINMAX = 89
+ OP_AVGADD = 90
+ OP_ABSDIFF = 91
+ OP_ABSADD = 92
+ OP_CPROP = 93
+ OP_BMASK = 94
+ OP_SVINDEX = 95
+ OP_FMVIS = 96
+ OP_FISHMV = 97
@unique
FRB = 14
CONST_SVD = 15 # for SVD-Form
CONST_SVDS = 16 # for SVDS-Form
+ CONST_XBI = 17
@unique
@unique
-class LdstLen(Enum):
+class LDSTLen(Enum):
NONE = 0
is1B = 1
is2B = 2
is4B = 4
is8B = 8
+# Backward compatibility
+LdstLen = LDSTLen
+
@unique
class LDSTMode(Enum):
# SPRs - Special-Purpose Registers. See V3.0B Figure 18 p971 and
# http://libre-riscv.org/openpower/isatables/sprs.csv
# http://bugs.libre-riscv.org/show_bug.cgi?id=261
+# http://bugs.libre-riscv.org/show_bug.cgi?id=859 - KAIVB
def get_spr_enum(full_file):
"""get_spr_enum - creates an Enum of SPRs, dynamically
short_list = {'PIDR', 'DAR', 'PRTBL', 'DSISR', 'SVSRR0', 'SVSTATE',
'SVSTATE0', 'SVSTATE1', 'SVSTATE2', 'SVSTATE3',
'SPRG0_priv', 'SPRG1_priv', 'SPRG2_priv', 'SPRG3_priv',
- 'SPRG3'
+ 'SPRG0', 'SPRG1', 'SPRG2', 'SPRG3', 'KAIVB',
+ # hmmm should not be including these, they are FAST regs
+ 'CTR', 'LR', 'TAR', 'SRR0', 'SRR1', 'XER', 'DEC', 'TB', 'TBU',
+ 'HSRR0', 'HSRR1', 'HSPRG0', 'HSPRG1',
}
spr_csv = []
for row in get_csv("sprs.csv"):
'CA32': 45
}
+MSRSpec = namedtuple("MSRSpec", ["dr", "pr", "sf"])
+
if __name__ == '__main__':
# find out what the heck is in SPR enum :)
print("sprs full", len(SPRfull))