-# SPDX-License: LGPLv3+
+# SPDX-License-Identifier: LGPL-3-or-later
# Copyright (C) 2020, 2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
# Copyright (C) 2020, Michael Nolan
def get_csv(name):
+ """gets a not-entirely-csv-file-formatted database, which allows comments
+ """
file_path = find_wiki_file(name)
with open(file_path, 'r') as csvfile:
+ csvfile = filter(lambda row: row[0] !='#', csvfile) # strip "#..."
reader = csv.DictReader(csvfile)
return list(reader)
SVD = 30 # Simple-V for LD/ST bit-reverse, variant of D-Form
SVDS = 31 # Simple-V for LD/ST bit-reverse, variant of DS-Form
SVM = 32 # Simple-V SHAPE mode - TEMPORARY TEMPORARY TEMPORARY
- SVRM = 33 # Simple-V REMAP mode - TEMPORARY TEMPORARY TEMPORARY
+ SVRM = 33 # Simple-V REMAP mode
+ TLI = 34 # ternlogi
+ XB = 35
+ BM2 = 36 # bmask
+ SVI = 37 # Simple-V Index Mode
+ VA2 = 38
+ SVC = 39
+ SVR = 40
# Simple-V svp64 fields https://libre-soc.org/openpower/sv/svp64/
FFIRST = 2
SATURATE = 3
PREDRES = 4
+ BRANCH = 5
+
+
+@unique
+class SVP64BCPredMode(Enum):
+ NONE = 0
+ MASKZERO = 1
+ MASKONE = 2
+
+
+@unique
+class SVP64BCVLSETMode(Enum):
+ NONE = 0
+ VL_INCL = 1
+ VL_EXCL = 2
+
+
+# note that these are chosen to be exactly the same as
+# SVP64 RM bit 4. ALL=1 => bit4=1
+@unique
+class SVP64BCGate(Enum):
+ ANY = 0
+ ALL = 1
+
+
+class SVP64BCCTRMode(Enum):
+ NONE = 0
+ TEST = 1
+ TEST_INV = 2
@unique
SIGNED = 1
UNSIGNED = 2
+
@unique
class SVP64LDSTmode(Enum):
NONE = 0
INDEXED = 1
ELSTRIDE = 2
UNITSTRIDE = 3
- BITREVERSE = 4
+ SHIFT = 4
# supported instructions: make sure to keep up-to-date with CSV files
"addg6s",
"and", "andc", "andi.", "andis.",
"attn",
+ "absdu", "absds", # AV bitmanip
+ "absdacs", "absdacu", # AV bitmanip
+ "avgadd", # AV bitmanip
"b", "bc", "bcctr", "bclr", "bctar",
+ "bmask", # AV bitmanip
"bpermd",
+ "cbcdtd",
"cdtbcd",
"cmp", "cmpb", "cmpeqb", "cmpi", "cmpl", "cmpli", "cmprb",
"cntlzd", "cntlzw", "cnttzd", "cnttzw",
+ "cprop", # AV bitmanip
"crand", "crandc", "creqv",
"crnand", "crnor", "cror", "crorc", "crxor",
"darn",
"divd", "divde", "divdeo", "divdeu",
"divdeuo", "divdo", "divdu", "divduo", "divw", "divwe", "divweo",
"divweu", "divweuo", "divwo", "divwu", "divwuo",
- "eqv",
+ "eieio", "eqv",
"extsb", "extsh", "extsw", "extswsli",
"fadd", "fadds", "fsub", "fsubs", # FP add / sub
"fcfids", "fcfidus", "fsqrts", "fres", "frsqrtes", # FP stuff
"fmul", "fmuls", "fdiv", "fdivs", # FP mul / div
"fmr", "fabs", "fnabs", "fneg", "fcpsgn", # FP move/abs/neg
"fsins", "fcoss", # FP SIN/COS
+ "fmvis", # FP load immediate
+ "fishmv", # Float Replace Lower-Half Single, Immediate
+ 'grev', 'grev.', 'grevi', 'grevi.',
+ 'grevw', 'grevw.', 'grevwi', 'grevwi.',
"hrfid", "icbi", "icbt", "isel", "isync",
- "lbarx", "lbz", "lbzu", "lbzux", "lbzx", # load byte
+ "lbarx", "lbz", "lbzcix", "lbzu", "lbzux", "lbzx", # load byte
"ld", "ldarx", "ldbrx", "ldu", "ldux", "ldx", # load double
- #"lbzbr", "lbzubr", # load byte SVP64 bit-reversed
- #"ldbr", "ldubr", # load double SVP64 bit-reversed
+ # "lbzbr", "lbzubr", # load byte SVP64 bit-reversed
+ # "ldbr", "ldubr", # load double SVP64 bit-reversed
"lfs", "lfsx", "lfsu", "lfsux", # FP load single
- "lfd", "lfdx", "lfdu", "lfdux", "lfiwzx", "lfiwax", # FP load double
+ "lfd", "lfdx", "lfdu", "lfdux", "lfiwzx", "lfiwax", # FP load double
"lha", "lharx", "lhau", "lhaux", "lhax", # load half
"lhbrx", "lhz", "lhzu", "lhzux", "lhzx", # more load half
- #"lhabr", "lhaubr", # load half SVP64 bit-reversed
- #"lhzbr", "lhzubr", # more load half SVP64 bit-reversed
+ # "lhabr", "lhaubr", # load half SVP64 bit-reversed
+ # "lhzbr", "lhzubr", # more load half SVP64 bit-reversed
"lwa", "lwarx", "lwaux", "lwax", "lwbrx", # load word
"lwz", "lwzcix", "lwzu", "lwzux", "lwzx", # more load word
- #"lwabr", # load word SVP64 bit-reversed
- #"lwzbr", "lwzubr", # more load word SVP64 bit-reversed
+ # "lwabr", # load word SVP64 bit-reversed
+ # "lwzbr", "lwzubr", # more load word SVP64 bit-reversed
"maddhd", "maddhdu", "maddld", # INT multiply-and-add
"mcrf", "mcrxr", "mcrxrx", "mfcr/mfocrf", # CR mvs
"mfmsr", "mfspr",
+ "mins", "maxs", "minu", "maxu", # AV bitmanip
"modsd", "modsw", "modud", "moduw",
"mtcrf/mtocrf", "mtmsr", "mtmsrd", "mtspr",
"mulhd", "mulhdu", "mulhw", "mulhwu", "mulld", "mulldo",
"rlwimi", "rlwinm", "rlwnm",
"setb",
"setvl", # https://libre-soc.org/openpower/sv/setvl
+ "svindex", # https://libre-soc.org/openpower/sv/remap
"svremap", # https://libre-soc.org/openpower/sv/remap - TEMPORARY
"svshape", # https://libre-soc.org/openpower/sv/remap
"svstep", # https://libre-soc.org/openpower/sv/setvl
"sraw", "srawi", "srd", "srw",
"stb", "stbcix", "stbcx", "stbu", "stbux", "stbx",
"std", "stdbrx", "stdcx", "stdu", "stdux", "stdx",
- "stfs", "stfsx", "stfsu", "stfux", # FP store single
+ "stfs", "stfsx", "stfsu", "stfux", "stfsux", # FP store single
"stfd", "stfdx", "stfdu", "stfdux", "stfiwx", # FP store double
"sth", "sthbrx", "sthcx", "sthu", "sthux", "sthx",
"stw", "stwbrx", "stwcx", "stwu", "stwux", "stwx",
"subf", "subfc", "subfco", "subfe", "subfeo", "subfic",
"subfme", "subfmeo", "subfo", "subfze", "subfzeo",
"sync",
+ "ternlogi",
"td", "tdi",
- "tlbie", "tlbiel",
+ "tlbie", "tlbiel", "tlbsync",
"tw", "twi",
+ "wait",
"xor", "xori", "xoris",
]
OP_TLBIE = 75
OP_SETVL = 76
OP_FPOP = 77 # temporary: replace with actual ops
- OP_FPOP_I = 78 # temporary: replace with actual ops
+ OP_FPOP_I = 78 # temporary: replace with actual ops
OP_FP_MADD = 79
OP_SVREMAP = 80
OP_SVSHAPE = 81
OP_SVSTEP = 82
OP_ADDG6S = 83
OP_CDTBCD = 84
+ OP_CBCDTD = 85
+ OP_TERNLOG = 86
+ OP_FETCH_FAILED = 87
+ OP_GREV = 88
+ OP_MINMAX = 89
+ OP_AVGADD = 90
+ OP_ABSDIFF = 91
+ OP_ABSADD = 92
+ OP_CPROP = 93
+ OP_BMASK = 94
+ OP_SVINDEX = 95
+ OP_FMVIS = 96
+ OP_FISHMV = 97
@unique
SPR = 12
RS = 13 # for shiftrot (M-Form)
FRB = 14
- CONST_SVD = 15 # for SVD-Form
- CONST_SVDS = 16 # for SVDS-Form
+ CONST_SVD = 15 # for SVD-Form
+ CONST_SVDS = 16 # for SVDS-Form
+ CONST_XBI = 17
@unique
FRS = 3
FRC = 4
RC = 5 # for SVP64 bit-reverse LD/ST
+ RT = 6 # for ternlog[i]
@unique
# SPRs - Special-Purpose Registers. See V3.0B Figure 18 p971 and
# http://libre-riscv.org/openpower/isatables/sprs.csv
# http://bugs.libre-riscv.org/show_bug.cgi?id=261
+# http://bugs.libre-riscv.org/show_bug.cgi?id=859 - KAIVB
def get_spr_enum(full_file):
"""get_spr_enum - creates an Enum of SPRs, dynamically
short_list = {'PIDR', 'DAR', 'PRTBL', 'DSISR', 'SVSRR0', 'SVSTATE',
'SVSTATE0', 'SVSTATE1', 'SVSTATE2', 'SVSTATE3',
'SPRG0_priv', 'SPRG1_priv', 'SPRG2_priv', 'SPRG3_priv',
- 'SPRG3'
- }
+ 'SPRG0', 'SPRG1', 'SPRG2', 'SPRG3', 'KAIVB',
+ # hmmm should not be including these, they are FAST regs
+ 'CTR', 'LR', 'TAR', 'SRR0', 'SRR1', 'XER', 'DEC', 'TB', 'TBU',
+ 'HSRR0', 'HSRR1', 'HSPRG0', 'HSPRG1',
+ }
spr_csv = []
for row in get_csv("sprs.csv"):
if full_file or row['SPR'] in short_list:
SPR = Enum('SPR', fields)
return SPR, spr_dict, spr_byname
+
SPRfull, spr_dict, spr_byname = get_spr_enum(full_file=True)
SPRreduced, _, _ = get_spr_enum(full_file=False)
'CA32': 45
}
+MSRSpec = namedtuple("MSRSpec", ["dr", "pr", "sf"])
+
if __name__ == '__main__':
# find out what the heck is in SPR enum :)
print("sprs full", len(SPRfull))
projects / openpower-isa.git / blobdiff