power_enums: add missing forms

[openpower-isa.git] / src / openpower / decoder / power_enums.py

diff --git a/src/openpower/decoder/power_enums.py b/src/openpower/decoder/power_enums.py
index 88279422834e6f5946161a8f75fb836e0b330133..9ef7b1910daaf572855bc0522a532ac80a3cd04a 100644 (file)
--- a/src/openpower/decoder/power_enums.py
+++ b/src/openpower/decoder/power_enums.py
@@ -1,4 +1,4 @@
-# SPDX-License: LGPLv3+
+# SPDX-License-Identifier: LGPL-3-or-later
 # Copyright (C) 2020, 2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 # Copyright (C) 2020, Michael Nolan
 
@@ -35,8 +35,11 @@ def find_wiki_file(name):
 
 
 def get_csv(name):
+    """gets a not-entirely-csv-file-formatted database, which allows comments
+    """
     file_path = find_wiki_file(name)
     with open(file_path, 'r') as csvfile:
+        csvfile = filter(lambda row: row[0] !='#', csvfile) # strip "#..."
         reader = csv.DictReader(csvfile)
         return list(reader)
 
@@ -119,8 +122,14 @@ class Form(Enum):
     SVD = 30  # Simple-V for LD/ST bit-reverse, variant of D-Form
     SVDS = 31  # Simple-V for LD/ST bit-reverse, variant of DS-Form
     SVM = 32  # Simple-V SHAPE mode - TEMPORARY TEMPORARY TEMPORARY
-    SVRM = 33  # Simple-V REMAP mode - TEMPORARY TEMPORARY TEMPORARY
+    SVRM = 33  # Simple-V REMAP mode
     TLI = 34  # ternlogi
+    XB = 35
+    BM2 = 36 # bmask
+    SVI = 37  # Simple-V Index Mode
+    VA2 = 38
+    SVC = 39
+    SVR = 40
 
 # Simple-V svp64 fields https://libre-soc.org/openpower/sv/svp64/
 
@@ -259,12 +268,17 @@ _insns = [
     "addg6s",
     "and", "andc", "andi.", "andis.",
     "attn",
+    "absdu", "absds",                         # AV bitmanip
+    "absdacs", "absdacu",                     # AV bitmanip
+    "avgadd",                                 # AV bitmanip
     "b", "bc", "bcctr", "bclr", "bctar",
+    "bmask",                                  # AV bitmanip
     "bpermd",
     "cbcdtd",
     "cdtbcd",
     "cmp", "cmpb", "cmpeqb", "cmpi", "cmpl", "cmpli", "cmprb",
     "cntlzd", "cntlzw", "cnttzd", "cnttzw",
+    "cprop", # AV bitmanip
     "crand", "crandc", "creqv",
     "crnand", "crnor", "cror", "crorc", "crxor",
     "darn",
@@ -272,7 +286,7 @@ _insns = [
     "divd", "divde", "divdeo", "divdeu",
     "divdeuo", "divdo", "divdu", "divduo", "divw", "divwe", "divweo",
     "divweu", "divweuo", "divwo", "divwu", "divwuo",
-    "eqv",
+    "eieio", "eqv",
     "extsb", "extsh", "extsw", "extswsli",
     "fadd", "fadds", "fsub", "fsubs",                   # FP add / sub
     "fcfids", "fcfidus", "fsqrts", "fres", "frsqrtes",  # FP stuff
@@ -283,8 +297,12 @@ _insns = [
     "fmul", "fmuls", "fdiv", "fdivs",                   # FP mul / div
     "fmr", "fabs", "fnabs", "fneg", "fcpsgn",           # FP move/abs/neg
     "fsins", "fcoss",                                   # FP SIN/COS
+    "fmvis",                                            # FP load immediate
+    "fishmv",                                           # Float Replace Lower-Half Single, Immediate
+    'grev', 'grev.', 'grevi', 'grevi.',
+    'grevw', 'grevw.', 'grevwi', 'grevwi.',
     "hrfid", "icbi", "icbt", "isel", "isync",
-    "lbarx", "lbz", "lbzu", "lbzux", "lbzx",            # load byte
+    "lbarx", "lbz", "lbzcix", "lbzu", "lbzux", "lbzx",  # load byte
     "ld", "ldarx", "ldbrx", "ldu", "ldux", "ldx",       # load double
     # "lbzbr", "lbzubr",  # load byte SVP64 bit-reversed
     # "ldbr", "ldubr",    # load double SVP64 bit-reversed
@@ -301,6 +319,7 @@ _insns = [
     "maddhd", "maddhdu", "maddld",                      # INT multiply-and-add
     "mcrf", "mcrxr", "mcrxrx", "mfcr/mfocrf",           # CR mvs
     "mfmsr", "mfspr",
+    "mins", "maxs", "minu", "maxu",                     # AV bitmanip
     "modsd", "modsw", "modud", "moduw",
     "mtcrf/mtocrf", "mtmsr", "mtmsrd", "mtspr",
     "mulhd", "mulhdu", "mulhw", "mulhwu", "mulld", "mulldo",
@@ -315,6 +334,7 @@ _insns = [
     "rlwimi", "rlwinm",    "rlwnm",
     "setb",
     "setvl",  # https://libre-soc.org/openpower/sv/setvl
+    "svindex",  # https://libre-soc.org/openpower/sv/remap
     "svremap",  # https://libre-soc.org/openpower/sv/remap - TEMPORARY
     "svshape",  # https://libre-soc.org/openpower/sv/remap
     "svstep",  # https://libre-soc.org/openpower/sv/setvl
@@ -332,8 +352,9 @@ _insns = [
     "sync",
     "ternlogi",
     "td", "tdi",
-    "tlbie", "tlbiel",
+    "tlbie", "tlbiel", "tlbsync",
     "tw", "twi",
+    "wait",
     "xor", "xori", "xoris",
 ]
 
@@ -436,7 +457,17 @@ class MicrOp(Enum):
     OP_CDTBCD = 84
     OP_CBCDTD = 85
     OP_TERNLOG = 86
-    OP_FETCH_FAILED = 86
+    OP_FETCH_FAILED = 87
+    OP_GREV = 88
+    OP_MINMAX = 89
+    OP_AVGADD = 90
+    OP_ABSDIFF = 91
+    OP_ABSADD = 92
+    OP_CPROP = 93
+    OP_BMASK = 94
+    OP_SVINDEX = 95
+    OP_FMVIS = 96
+    OP_FISHMV = 97
 
 
 @unique
@@ -469,6 +500,7 @@ class In2Sel(Enum):
     FRB = 14
     CONST_SVD = 15  # for SVD-Form
     CONST_SVDS = 16  # for SVDS-Form
+    CONST_XBI = 17
 
 
 @unique
@@ -550,6 +582,7 @@ class CROutSel(Enum):
 # SPRs - Special-Purpose Registers.  See V3.0B Figure 18 p971 and
 # http://libre-riscv.org/openpower/isatables/sprs.csv
 # http://bugs.libre-riscv.org/show_bug.cgi?id=261
+# http://bugs.libre-riscv.org/show_bug.cgi?id=859 - KAIVB
 
 def get_spr_enum(full_file):
     """get_spr_enum - creates an Enum of SPRs, dynamically
@@ -559,7 +592,10 @@ def get_spr_enum(full_file):
     short_list = {'PIDR', 'DAR', 'PRTBL', 'DSISR', 'SVSRR0', 'SVSTATE',
                   'SVSTATE0', 'SVSTATE1', 'SVSTATE2', 'SVSTATE3',
                   'SPRG0_priv', 'SPRG1_priv', 'SPRG2_priv', 'SPRG3_priv',
-                  'SPRG3'
+                  'SPRG0', 'SPRG1', 'SPRG2', 'SPRG3', 'KAIVB',
+                  # hmmm should not be including these, they are FAST regs
+                  'CTR', 'LR', 'TAR', 'SRR0', 'SRR1', 'XER', 'DEC', 'TB', 'TBU',
+                  'HSRR0', 'HSRR1', 'HSPRG0', 'HSPRG1',
                   }
     spr_csv = []
     for row in get_csv("sprs.csv"):
@@ -591,6 +627,8 @@ XER_bits = {
     'CA32': 45
 }
 
+MSRSpec = namedtuple("MSRSpec", ["dr", "pr", "sf"])
+
 if __name__ == '__main__':
     # find out what the heck is in SPR enum :)
     print("sprs full", len(SPRfull))