sv.bc test jumping to wrong location (offset 0xc not 0x8)

[openpower-isa.git] / src / openpower / decoder / power_enums.py

diff --git a/src/openpower/decoder/power_enums.py b/src/openpower/decoder/power_enums.py
index 0788642b0c338db1e1b0ba11bfe4b9bbcbf49434..eee86b949e7d18675b798caf6289f2152761223e 100644 (file)
--- a/src/openpower/decoder/power_enums.py
+++ b/src/openpower/decoder/power_enums.py
@@ -116,6 +116,10 @@ class Form(Enum):
     Z22 = 27
     Z23 = 28
     SVL = 29  # Simple-V for setvl instruction
+    SVD = 30  # Simple-V for LD/ST bit-reverse, variant of D-Form
+    SVDS = 31  # Simple-V for LD/ST bit-reverse, variant of DS-Form
+    SVM = 32  # Simple-V SHAPE mode - TEMPORARY TEMPORARY TEMPORARY
+    SVRM = 33  # Simple-V REMAP mode - TEMPORARY TEMPORARY TEMPORARY
 
 # Simple-V svp64 fields https://libre-soc.org/openpower/sv/svp64/
 
@@ -182,6 +186,35 @@ class SVP64RMMode(Enum):
     FFIRST = 2
     SATURATE = 3
     PREDRES = 4
+    BRANCH = 5
+
+
+@unique
+class SVP64BCPredMode(Enum):
+    NONE = 0
+    MASKZERO = 1
+    MASKONE = 2
+
+@unique
+class SVP64BCVLSETMode(Enum):
+    NONE = 0
+    VL_INCL = 1
+    VL_EXCL = 2
+
+
+# note that these are chosen to be exactly the same as
+# SVP64 RM bit 4.  ALL=1 => bit4=1
+@unique
+class SVP64BCGate(Enum):
+    ANY = 0
+    ALL = 1
+
+
+@unique
+class SVP64BCStep(Enum):
+    NONE = 0
+    STEP = 1
+    STEP_RC = 2
 
 
 @unique
@@ -212,7 +245,7 @@ class SVP64LDSTmode(Enum):
     INDEXED = 1
     ELSTRIDE = 2
     UNITSTRIDE = 3
-    BITREVERSE = 4
+    SHIFT = 4
 
 
 # supported instructions: make sure to keep up-to-date with CSV files
@@ -221,10 +254,13 @@ _insns = [
     "NONE", "add", "addc", "addco", "adde", "addeo",
     "addi", "addic", "addic.", "addis",
     "addme", "addmeo", "addo", "addze", "addzeo",
+    "addg6s",
     "and", "andc", "andi.", "andis.",
     "attn",
     "b", "bc", "bcctr", "bclr", "bctar",
     "bpermd",
+    "cbcdtd",
+    "cdtbcd",
     "cmp", "cmpb", "cmpeqb", "cmpi", "cmpl", "cmpli", "cmprb",
     "cntlzd", "cntlzw", "cnttzd", "cnttzw",
     "crand", "crandc", "creqv",
@@ -238,18 +274,28 @@ _insns = [
     "extsb", "extsh", "extsw", "extswsli",
     "fadd", "fadds", "fsub", "fsubs",                   # FP add / sub
     "fcfids", "fcfidus", "fsqrts", "fres", "frsqrtes",  # FP stuff
+    "fdmadds",                                          # DCT FP 3-arg
     "fmsubs", "fmadds", "fnmsubs", "fnmadds",           # FP 3-arg
+    "ffadds", "ffsubs", "ffmuls", "ffdivs",             # FFT FP 2-arg
+    "ffmsubs", "ffmadds", "ffnmsubs", "ffnmadds",       # FFT FP 3-arg
     "fmul", "fmuls", "fdiv", "fdivs",                   # FP mul / div
     "fmr", "fabs", "fnabs", "fneg", "fcpsgn",           # FP move/abs/neg
+    "fsins", "fcoss",                                   # FP SIN/COS
     "hrfid", "icbi", "icbt", "isel", "isync",
     "lbarx", "lbz", "lbzu", "lbzux", "lbzx",            # load byte
     "ld", "ldarx", "ldbrx", "ldu", "ldux", "ldx",       # load double
+    #"lbzbr", "lbzubr",  # load byte SVP64 bit-reversed
+    #"ldbr", "ldubr",    # load double SVP64 bit-reversed
     "lfs", "lfsx", "lfsu", "lfsux",                     # FP load single
     "lfd", "lfdx", "lfdu", "lfdux", "lfiwzx", "lfiwax", # FP load double
     "lha", "lharx", "lhau", "lhaux", "lhax",            # load half
     "lhbrx", "lhz", "lhzu", "lhzux", "lhzx",            # more load half
+    #"lhabr", "lhaubr",  # load half SVP64 bit-reversed
+    #"lhzbr", "lhzubr",  # more load half SVP64 bit-reversed
     "lwa", "lwarx", "lwaux", "lwax", "lwbrx",           # load word
     "lwz", "lwzcix", "lwzu", "lwzux", "lwzx",           # more load word
+    #"lwabr",           # load word SVP64 bit-reversed
+    #"lwzbr", "lwzubr", # more load word SVP64 bit-reversed
     "maddhd", "maddhdu", "maddld",                      # INT multiply-and-add
     "mcrf", "mcrxr", "mcrxrx", "mfcr/mfocrf",           # CR mvs
     "mfmsr", "mfspr",
@@ -267,6 +313,9 @@ _insns = [
     "rlwimi", "rlwinm",    "rlwnm",
     "setb",
     "setvl",  # https://libre-soc.org/openpower/sv/setvl
+    "svremap",  # https://libre-soc.org/openpower/sv/remap - TEMPORARY
+    "svshape",  # https://libre-soc.org/openpower/sv/remap
+    "svstep",  # https://libre-soc.org/openpower/sv/setvl
     "sim_cfg",
     "slbia", "sld", "slw", "srad", "sradi",
     "sraw", "srawi", "srd", "srw",
@@ -292,6 +341,9 @@ for i, insn in enumerate(_insns):
     insns[i] = insn
     asmidx[insn] = i
 
+# must be long enough to cover all instructions
+asmlen = len(_insns).bit_length()
+
 # Internal Operation numbering.  Add new opcodes here (FPADD, FPMUL etc.)
 
 
@@ -373,6 +425,13 @@ class MicrOp(Enum):
     OP_SETVL = 76
     OP_FPOP = 77  # temporary: replace with actual ops
     OP_FPOP_I = 78 # temporary: replace with actual ops
+    OP_FP_MADD = 79
+    OP_SVREMAP = 80
+    OP_SVSHAPE = 81
+    OP_SVSTEP = 82
+    OP_ADDG6S = 83
+    OP_CDTBCD = 84
+    OP_CBCDTD = 85
 
 
 @unique
@@ -403,6 +462,8 @@ class In2Sel(Enum):
     SPR = 12
     RS = 13  # for shiftrot (M-Form)
     FRB = 14
+    CONST_SVD = 15 # for SVD-Form
+    CONST_SVDS = 16 # for SVDS-Form
 
 
 @unique
@@ -412,6 +473,7 @@ class In3Sel(Enum):
     RB = 2  # for shiftrot (M-Form)
     FRS = 3
     FRC = 4
+    RC = 5  # for SVP64 bit-reverse LD/ST
 
 
 @unique
@@ -422,6 +484,7 @@ class OutSel(Enum):
     SPR = 3
     RT_OR_ZERO = 4
     FRT = 5
+    FRS = 6
 
 
 @unique
@@ -488,6 +551,7 @@ def get_spr_enum(full_file):
     this saves drastically on the size of the regfile
     """
     short_list = {'PIDR', 'DAR', 'PRTBL', 'DSISR', 'SVSRR0', 'SVSTATE',
+                  'SVSTATE0', 'SVSTATE1', 'SVSTATE2', 'SVSTATE3',
                   'SPRG0_priv', 'SPRG1_priv', 'SPRG2_priv', 'SPRG3_priv',
                   'SPRG3'
                  }