FFIRST = 2
SATURATE = 3
PREDRES = 4
+ BRANCH = 5
+
+
+@unique
+class SVP64BCPredMode(Enum):
+ NONE = 0
+ MASKZERO = 1
+ MASKONE = 2
+
+@unique
+class SVP64BCVLSETMode(Enum):
+ NONE = 0
+ VL_INCL = 1
+ VL_EXCL = 2
+
+
+# note that these are chosen to be exactly the same as
+# SVP64 RM bit 4. ALL=1 => bit4=1
+@unique
+class SVP64BCGate(Enum):
+ ANY = 0
+ ALL = 1
+
+
+@unique
+class SVP64BCStep(Enum):
+ NONE = 0
+ STEP = 1
+ STEP_RC = 2
@unique
INDEXED = 1
ELSTRIDE = 2
UNITSTRIDE = 3
- BITREVERSE = 4
+ SHIFT = 4
# supported instructions: make sure to keep up-to-date with CSV files
"NONE", "add", "addc", "addco", "adde", "addeo",
"addi", "addic", "addic.", "addis",
"addme", "addmeo", "addo", "addze", "addzeo",
+ "addg6s",
"and", "andc", "andi.", "andis.",
"attn",
"b", "bc", "bcctr", "bclr", "bctar",
"bpermd",
+ "cbcdtd",
+ "cdtbcd",
"cmp", "cmpb", "cmpeqb", "cmpi", "cmpl", "cmpli", "cmprb",
"cntlzd", "cntlzw", "cnttzd", "cnttzw",
"crand", "crandc", "creqv",
"setvl", # https://libre-soc.org/openpower/sv/setvl
"svremap", # https://libre-soc.org/openpower/sv/remap - TEMPORARY
"svshape", # https://libre-soc.org/openpower/sv/remap
+ "svstep", # https://libre-soc.org/openpower/sv/setvl
"sim_cfg",
"slbia", "sld", "slw", "srad", "sradi",
"sraw", "srawi", "srd", "srw",
OP_FP_MADD = 79
OP_SVREMAP = 80
OP_SVSHAPE = 81
+ OP_SVSTEP = 82
+ OP_ADDG6S = 83
+ OP_CDTBCD = 84
+ OP_CBCDTD = 85
@unique