SVDS = 31 # Simple-V for LD/ST bit-reverse, variant of DS-Form
SVM = 32 # Simple-V SHAPE mode - TEMPORARY TEMPORARY TEMPORARY
SVRM = 33 # Simple-V REMAP mode - TEMPORARY TEMPORARY TEMPORARY
- TI = 34 # ternaryi
+ TLI = 34 # ternlogi
# Simple-V svp64 fields https://libre-soc.org/openpower/sv/svp64/
"subf", "subfc", "subfco", "subfe", "subfeo", "subfic",
"subfme", "subfmeo", "subfo", "subfze", "subfzeo",
"sync",
- "ternaryi",
+ "ternlogi",
"td", "tdi",
"tlbie", "tlbiel",
"tw", "twi",
OP_ADDG6S = 83
OP_CDTBCD = 84
OP_CBCDTD = 85
- OP_TERNARYI = 86
+ OP_TERNLOG = 86
+ OP_FETCH_FAILED = 87
@unique
FRS = 3
FRC = 4
RC = 5 # for SVP64 bit-reverse LD/ST
- CONST_TII = 6 # for ternaryi - XXX TODO: REMOVE THIS (from CSV, first)
- RT = 7 # for ternary
+ RT = 6 # for ternlog[i]
@unique
short_list = {'PIDR', 'DAR', 'PRTBL', 'DSISR', 'SVSRR0', 'SVSTATE',
'SVSTATE0', 'SVSTATE1', 'SVSTATE2', 'SVSTATE3',
'SPRG0_priv', 'SPRG1_priv', 'SPRG2_priv', 'SPRG3_priv',
- 'SPRG3'
+ 'SPRG3',
+ # hmmm should not be including these, they are FAST regs
+ 'CTR', 'LR', 'TAR', 'SRR0', 'SRR1', 'XER', 'DEC', 'TB', 'TBU',
}
spr_csv = []
for row in get_csv("sprs.csv"):
'CA32': 45
}
+MSRSpec = namedtuple("MSRSpec", ["dr", "pr", "sf"])
+
if __name__ == '__main__':
# find out what the heck is in SPR enum :)
print("sprs full", len(SPRfull))