code cleanup / comments

[openpower-isa.git] / src / openpower / decoder / power_enums.py

diff --git a/src/openpower/decoder/power_enums.py b/src/openpower/decoder/power_enums.py
index e631f374e70c4823e0f6030b08bbc0dc1ae03ef4..f0392d584f1607ad13b83398b18501f739ea4834 100644 (file)
--- a/src/openpower/decoder/power_enums.py
+++ b/src/openpower/decoder/power_enums.py
@@ -120,6 +120,7 @@ class Form(Enum):
     SVDS = 31  # Simple-V for LD/ST bit-reverse, variant of DS-Form
     SVM = 32  # Simple-V SHAPE mode - TEMPORARY TEMPORARY TEMPORARY
     SVRM = 33  # Simple-V REMAP mode - TEMPORARY TEMPORARY TEMPORARY
+    TLI = 34  # ternlogi
 
 # Simple-V svp64 fields https://libre-soc.org/openpower/sv/svp64/
 
@@ -186,6 +187,35 @@ class SVP64RMMode(Enum):
     FFIRST = 2
     SATURATE = 3
     PREDRES = 4
+    BRANCH = 5
+
+
+@unique
+class SVP64BCPredMode(Enum):
+    NONE = 0
+    MASKZERO = 1
+    MASKONE = 2
+
+
+@unique
+class SVP64BCVLSETMode(Enum):
+    NONE = 0
+    VL_INCL = 1
+    VL_EXCL = 2
+
+
+# note that these are chosen to be exactly the same as
+# SVP64 RM bit 4.  ALL=1 => bit4=1
+@unique
+class SVP64BCGate(Enum):
+    ANY = 0
+    ALL = 1
+
+
+class SVP64BCCTRMode(Enum):
+    NONE = 0
+    TEST = 1
+    TEST_INV = 2
 
 
 @unique
@@ -210,13 +240,14 @@ class SVP64sat(Enum):
     SIGNED = 1
     UNSIGNED = 2
 
+
 @unique
 class SVP64LDSTmode(Enum):
     NONE = 0
     INDEXED = 1
     ELSTRIDE = 2
     UNITSTRIDE = 3
-    BITREVERSE = 4
+    SHIFT = 4
 
 
 # supported instructions: make sure to keep up-to-date with CSV files
@@ -230,6 +261,8 @@ _insns = [
     "attn",
     "b", "bc", "bcctr", "bclr", "bctar",
     "bpermd",
+    "cbcdtd",
+    "cdtbcd",
     "cmp", "cmpb", "cmpeqb", "cmpi", "cmpl", "cmpli", "cmprb",
     "cntlzd", "cntlzw", "cnttzd", "cnttzw",
     "crand", "crandc", "creqv",
@@ -253,18 +286,18 @@ _insns = [
     "hrfid", "icbi", "icbt", "isel", "isync",
     "lbarx", "lbz", "lbzu", "lbzux", "lbzx",            # load byte
     "ld", "ldarx", "ldbrx", "ldu", "ldux", "ldx",       # load double
-    #"lbzbr", "lbzubr",  # load byte SVP64 bit-reversed
-    #"ldbr", "ldubr",    # load double SVP64 bit-reversed
+    # "lbzbr", "lbzubr",  # load byte SVP64 bit-reversed
+    # "ldbr", "ldubr",    # load double SVP64 bit-reversed
     "lfs", "lfsx", "lfsu", "lfsux",                     # FP load single
-    "lfd", "lfdx", "lfdu", "lfdux", "lfiwzx", "lfiwax", # FP load double
+    "lfd", "lfdx", "lfdu", "lfdux", "lfiwzx", "lfiwax",  # FP load double
     "lha", "lharx", "lhau", "lhaux", "lhax",            # load half
     "lhbrx", "lhz", "lhzu", "lhzux", "lhzx",            # more load half
-    #"lhabr", "lhaubr",  # load half SVP64 bit-reversed
-    #"lhzbr", "lhzubr",  # more load half SVP64 bit-reversed
+    # "lhabr", "lhaubr",  # load half SVP64 bit-reversed
+    # "lhzbr", "lhzubr",  # more load half SVP64 bit-reversed
     "lwa", "lwarx", "lwaux", "lwax", "lwbrx",           # load word
     "lwz", "lwzcix", "lwzu", "lwzux", "lwzx",           # more load word
-    #"lwabr",           # load word SVP64 bit-reversed
-    #"lwzbr", "lwzubr", # more load word SVP64 bit-reversed
+    # "lwabr",           # load word SVP64 bit-reversed
+    # "lwzbr", "lwzubr", # more load word SVP64 bit-reversed
     "maddhd", "maddhdu", "maddld",                      # INT multiply-and-add
     "mcrf", "mcrxr", "mcrxrx", "mfcr/mfocrf",           # CR mvs
     "mfmsr", "mfspr",
@@ -290,13 +323,14 @@ _insns = [
     "sraw", "srawi", "srd", "srw",
     "stb", "stbcix", "stbcx", "stbu", "stbux", "stbx",
     "std", "stdbrx", "stdcx", "stdu", "stdux", "stdx",
-    "stfs", "stfsx", "stfsu", "stfux",                  # FP store single
+    "stfs", "stfsx", "stfsu", "stfux", "stfsux",        # FP store single
     "stfd", "stfdx", "stfdu", "stfdux", "stfiwx",       # FP store double
     "sth", "sthbrx", "sthcx", "sthu", "sthux", "sthx",
     "stw", "stwbrx", "stwcx", "stwu", "stwux", "stwx",
     "subf", "subfc", "subfco", "subfe", "subfeo", "subfic",
     "subfme", "subfmeo", "subfo", "subfze", "subfzeo",
     "sync",
+    "ternlogi",
     "td", "tdi",
     "tlbie", "tlbiel",
     "tw", "twi",
@@ -393,12 +427,16 @@ class MicrOp(Enum):
     OP_TLBIE = 75
     OP_SETVL = 76
     OP_FPOP = 77  # temporary: replace with actual ops
-    OP_FPOP_I = 78 # temporary: replace with actual ops
+    OP_FPOP_I = 78  # temporary: replace with actual ops
     OP_FP_MADD = 79
     OP_SVREMAP = 80
     OP_SVSHAPE = 81
     OP_SVSTEP = 82
     OP_ADDG6S = 83
+    OP_CDTBCD = 84
+    OP_CBCDTD = 85
+    OP_TERNLOG = 86
+    OP_FETCH_FAILED = 87
 
 
 @unique
@@ -429,8 +467,8 @@ class In2Sel(Enum):
     SPR = 12
     RS = 13  # for shiftrot (M-Form)
     FRB = 14
-    CONST_SVD = 15 # for SVD-Form
-    CONST_SVDS = 16 # for SVDS-Form
+    CONST_SVD = 15  # for SVD-Form
+    CONST_SVDS = 16  # for SVDS-Form
 
 
 @unique
@@ -441,6 +479,7 @@ class In3Sel(Enum):
     FRS = 3
     FRC = 4
     RC = 5  # for SVP64 bit-reverse LD/ST
+    RT = 6  # for ternlog[i]
 
 
 @unique
@@ -520,8 +559,10 @@ def get_spr_enum(full_file):
     short_list = {'PIDR', 'DAR', 'PRTBL', 'DSISR', 'SVSRR0', 'SVSTATE',
                   'SVSTATE0', 'SVSTATE1', 'SVSTATE2', 'SVSTATE3',
                   'SPRG0_priv', 'SPRG1_priv', 'SPRG2_priv', 'SPRG3_priv',
-                  'SPRG3'
-                 }
+                  'SPRG3',
+                  # hmmm should not be including these, they are FAST regs
+                  'CTR', 'LR', 'TAR', 'SRR0', 'SRR1', 'XER', 'DEC', 'TB', 'TBU',
+                  }
     spr_csv = []
     for row in get_csv("sprs.csv"):
         if full_file or row['SPR'] in short_list:
@@ -540,6 +581,7 @@ def get_spr_enum(full_file):
     SPR = Enum('SPR', fields)
     return SPR, spr_dict, spr_byname
 
+
 SPRfull, spr_dict, spr_byname = get_spr_enum(full_file=True)
 SPRreduced, _, _ = get_spr_enum(full_file=False)
 
@@ -551,6 +593,8 @@ XER_bits = {
     'CA32': 45
 }
 
+MSRSpec = namedtuple("MSRSpec", ["dr", "pr", "sf"])
+
 if __name__ == '__main__':
     # find out what the heck is in SPR enum :)
     print("sprs full", len(SPRfull))