power_insn: stricter reg type check

[openpower-isa.git] / src / openpower / decoder / power_fieldsn.py

diff --git a/src/openpower/decoder/power_fieldsn.py b/src/openpower/decoder/power_fieldsn.py
index 852dd15b079cc88a1b555f71d216107ce2d9c7a1..982bd64586e7098863aefe11a816ec30afe6eb95 100644 (file)
--- a/src/openpower/decoder/power_fieldsn.py
+++ b/src/openpower/decoder/power_fieldsn.py
@@ -1,9 +1,11 @@
 from collections import OrderedDict
-from soc.decoder.power_fields import DecodeFields, BitRange
+from openpower.decoder.power_fields import DecodeFields
 from nmigen import Module, Elaboratable, Signal, Cat
 from nmigen.cli import rtlil
 from copy import deepcopy
 
+from openpower.decoder.selectable_int import BitRange
+
 
 class SignalBitRange(BitRange):
     def __init__(self, signal):