In3Sel as _In3Sel,
OutSel as _OutSel,
CRInSel as _CRInSel,
+ CRIn2Sel as _CRIn2Sel,
CROutSel as _CROutSel,
LDSTLen as _LDSTLen,
LDSTMode as _LDSTMode,
CryIn as _CryIn,
Form as _Form,
SVEtype as _SVEtype,
+ SVmask_src as _SVmask_src,
SVMode as _SVMode,
SVPtype as _SVPtype,
SVExtra as _SVExtra,
@_functools.total_ordering
@_dataclasses.dataclass(eq=True, frozen=True)
class Opcode:
- class Value(int):
- def __repr__(self):
- if self.bit_length() <= 32:
- return f"0x{self:08x}"
- else:
- return f"0x{self:016x}"
+ class Integer(int):
+ def __new__(cls, value):
+ if isinstance(value, str):
+ value = int(value, 0)
+ if not isinstance(value, int):
+ raise ValueError(value)
- class Mask(int):
- def bit_count(self):
- return bin(self).count("1")
+ if value.bit_length() > 64:
+ raise ValueError(value)
+
+ return super().__new__(cls, value)
+
+ def __str__(self):
+ return super().__repr__()
def __repr__(self):
- if self.bit_length() <= 32:
- return f"0x{self:08x}"
- else:
- return f"0x{self:016x}"
+ return f"{self:0{self.bit_length()}b}"
+
+ def bit_length(self):
+ if super().bit_length() > 32:
+ return 64
+ return 32
+
+ class Value(Integer):
+ pass
+
+ class Mask(Integer):
+ pass
value: Value
mask: Mask
return ((self.value, self.mask) < (other.value, other.mask))
def __post_init__(self):
- (value, mask) = (self.value, self.mask)
-
- if isinstance(value, Opcode):
- if mask is not None:
- raise ValueError(mask)
- (value, mask) = (value.value, value.mask)
- elif isinstance(value, str):
- if mask is not None:
- raise ValueError(mask)
- value = int(value, 0)
-
- if not isinstance(value, int):
- raise ValueError(value)
- if not isinstance(mask, int):
- raise ValueError(mask)
+ if self.value.bit_length() != self.mask.bit_length():
+ raise ValueError("bit length mismatch")
- object.__setattr__(self, "value", self.__class__.Value(value))
- object.__setattr__(self, "mask", self.__class__.Mask(mask))
+ def __repr__(self):
+ def pattern(value, mask, bit_length):
+ for bit in range(bit_length):
+ if ((mask & (1 << (bit_length - bit - 1))) == 0):
+ yield "-"
+ elif (value & (1 << (bit_length - bit - 1))):
+ yield "1"
+ else:
+ yield "0"
+
+ return "".join(pattern(self.value, self.mask, self.value.bit_length()))
class IntegerOpcode(Opcode):
mask = int(("1" * len(value[2:])), 2)
else:
mask = 0b111111
- value = int(value, 0)
+
+ value = Opcode.Value(value)
+ mask = Opcode.Mask(mask)
return super().__init__(value=value, mask=mask)
class PatternOpcode(Opcode):
- def __init__(self, value):
- (pattern, value, mask) = (value, 0, 0)
+ def __init__(self, pattern):
+ if not isinstance(pattern, str):
+ raise ValueError(pattern)
+ (value, mask) = (0, 0)
for symbol in pattern:
if symbol not in {"0", "1", "-"}:
raise ValueError(pattern)
value >>= 1
mask >>= 1
+ value = Opcode.Value(value)
+ mask = Opcode.Mask(mask)
+
return super().__init__(value=value, mask=mask)
in3: _In3Sel = _In3Sel.NONE
out: _OutSel = _OutSel.NONE
cr_in: _CRInSel = _CRInSel.NONE
+ cr_in2: _CRIn2Sel = _CRIn2Sel.NONE
cr_out: _CROutSel = _CROutSel.NONE
cry_in: _CryIn = _CryIn.ZERO
ldst_len: _LDSTLen = _LDSTLen.NONE
typemap = {field.name:field.type for field in _dataclasses.fields(cls)}
typemap["opcode"] = opcode_cls
+ if record["CR in"] == "BA_BB":
+ record["cr_in"] = "BA"
+ record["cr_in2"] = "BB"
+ del record["CR in"]
+
flags = set()
for flag in frozenset(PPCRecord.Flags):
if bool(record.pop(flag, "")):
return frozenset(self.comment.split("=")[-1].split("/"))
-class PPCMultiRecord(frozenset):
- @cached_property
- def unified(self):
- def merge(lhs, rhs):
- value = 0
- mask = 0
- lvalue = lhs.opcode.value
- rvalue = rhs.opcode.value
- lmask = lhs.opcode.mask
- rmask = rhs.opcode.mask
- bits = max(lmask.bit_length(), rmask.bit_length())
- for bit in range(bits):
- lvstate = ((lvalue & (1 << bit)) != 0)
- rvstate = ((rvalue & (1 << bit)) != 0)
- lmstate = ((lmask & (1 << bit)) != 0)
- rmstate = ((rmask & (1 << bit)) != 0)
- vstate = lvstate
- mstate = True
- if (not lmstate or not rmstate) or (lvstate != rvstate):
- vstate = 0
- mstate = 0
- value |= (vstate << bit)
- mask |= (mstate << bit)
-
- opcode = Opcode(value=value, mask=mask)
-
- return _dataclasses.replace(lhs, opcode=opcode)
-
- return _functools.reduce(merge, self)
-
+class PPCMultiRecord(tuple):
def __getattr__(self, attr):
- return getattr(self.unified, attr)
+ if attr == "opcode":
+ raise AttributeError(attr)
+ return getattr(self[0], attr)
@_dataclasses.dataclass(eq=True, frozen=True)
name: str
ptype: _SVPtype = _SVPtype.NONE
etype: _SVEtype = _SVEtype.NONE
+ msrc: _SVmask_src = _SVmask_src.NO # MASK_SRC is active
in1: _In1Sel = _In1Sel.NONE
in2: _In2Sel = _In2Sel.NONE
in3: _In3Sel = _In3Sel.NONE
out: _OutSel = _OutSel.NONE
out2: _OutSel = _OutSel.NONE
cr_in: _CRInSel = _CRInSel.NONE
+ cr_in2: _CRIn2Sel = _CRIn2Sel.NONE
cr_out: _CROutSel = _CROutSel.NONE
extra: ExtraMap = ExtraMap()
conditions: str = ""
"CONDITIONS": "conditions",
"Ptype": "ptype",
"Etype": "etype",
+ "SM": "msrc",
"CR in": "cr_in",
"CR out": "cr_out",
}
@classmethod
def CSV(cls, record):
- for key in ("in1", "in2", "in3", "out", "out2", "CR in", "CR out"):
+ for key in frozenset({
+ "in1", "in2", "in3", "CR in",
+ "out", "out2", "CR out",
+ }):
value = record[key]
if value == "0":
record[key] = "NONE"
+ if record["CR in"] == "BA_BB":
+ record["cr_in"] = "BA"
+ record["cr_in2"] = "BB"
+ del record["CR in"]
+
extra = []
for idx in range(0, 4):
extra.append(record.pop(f"{idx}"))
)
if key not in frozenset({
- "in1", "in2", "in3", "cr_in",
+ "in1", "in2", "in3", "cr_in", "cr_in2",
"out", "out2", "cr_out",
}):
raise KeyError(key)
yield str(int(value))
+class SignedOperand(DynamicOperand):
+ def disassemble(self, insn, record,
+ verbosity=Verbosity.NORMAL, indent=""):
+ span = self.span(record=record)
+ if isinstance(insn, SVP64Instruction):
+ span = tuple(map(lambda bit: (bit + 32), span))
+ value = insn[span]
+
+ if verbosity >= Verbosity.VERBOSE:
+ span = map(str, span)
+ yield f"{indent}{self.name}"
+ yield f"{indent}{indent}{int(value):0{value.bits}b}"
+ yield f"{indent}{indent}{', '.join(span)}"
+ else:
+ yield str(value.to_signed_int())
+
+
@_dataclasses.dataclass(eq=True, frozen=True)
class StaticOperand(Operand):
value: int
class RegisterOperand(DynamicOperand):
- def spec(self, insn, record, merge):
+ def sv_spec_enter(self, value, span):
+ return (value, span)
+
+ def sv_spec_leave(self, value, span, origin_value, origin_span):
+ return (value, span)
+
+ def spec(self, insn, record):
vector = False
span = self.span(record=record)
if isinstance(insn, SVP64Instruction):
span = tuple(map(str, span))
if isinstance(insn, SVP64Instruction):
+ (origin_value, origin_span) = (value, span)
+ (value, span) = self.sv_spec_enter(value=value, span=span)
+
extra_idx = self.extra_idx(record=record)
if extra_idx is _SVExtra.NONE:
return (vector, value, span)
else:
raise ValueError(record.etype)
- (value, span) = merge(vector, value, span, spec, spec_span)
+ vector_shift = (2 + (5 - value.bits))
+ scalar_shift = value.bits
+ spec_shift = (5 - value.bits)
+
+ bits = (len(span) + len(spec_span))
+ value = _SelectableInt(value=value.value, bits=bits)
+ spec = _SelectableInt(value=spec.value, bits=bits)
+ if vector:
+ value = ((value << vector_shift) | (spec << spec_shift))
+ span = (span + spec_span + ((spec_shift * ('{0}',))))
+ else:
+ value = ((spec << scalar_shift) | value)
+ span = ((spec_shift * ('{0}',)) + spec_span + span)
+
+ (value, span) = self.sv_spec_leave(value=value, span=span,
+ origin_value=origin_value, origin_span=origin_span)
return (vector, value, span)
def extra_idx(self, record):
for key in frozenset({
- "in1", "in2", "in3", "cr_in",
+ "in1", "in2", "in3", "cr_in", "cr_in2",
"out", "out2", "cr_out",
}):
extra_reg = record.svp64.extra_reg(key=key)
yield f"{vector}{prefix}{int(value)}"
-class GPRFPROperand(RegisterOperand):
- def spec(self, insn, record):
- def merge(vector, value, span, spec, spec_span):
- bits = (len(span) + len(spec_span))
- value = _SelectableInt(value=value.value, bits=bits)
- spec = _SelectableInt(value=spec.value, bits=bits)
- if vector:
- value = ((value << 2) | spec)
- span = (span + spec_span)
- else:
- value = ((spec << 5) | value)
- span = (spec_span + span)
-
- return (value, span)
-
- return super().spec(insn=insn, record=record, merge=merge)
-
-
-class GPROperand(GPRFPROperand):
+class GPROperand(RegisterOperand):
def disassemble(self, insn, record,
verbosity=Verbosity.NORMAL, indent=""):
prefix = "" if (verbosity <= Verbosity.SHORT) else "r"
verbosity=verbosity, indent=indent)
-class FPROperand(GPRFPROperand):
+class FPROperand(RegisterOperand):
def disassemble(self, insn, record,
verbosity=Verbosity.NORMAL, indent=""):
prefix = "" if (verbosity <= Verbosity.SHORT) else "f"
verbosity=verbosity, indent=indent)
-class DynamicOperandCR(RegisterOperand):
- def spec(self, insn, record):
- def merge(vector, value, span, spec, spec_span):
- bits = (len(span) + len(spec_span))
- value = _SelectableInt(value=value.value, bits=bits)
- spec = _SelectableInt(value=spec.value, bits=bits)
- if vector:
- dst_value = []
- dst_span = []
- table = (
- (value, span, (0, 1, 2)),
- (spec, spec_span, (0, 1)),
- (value, span, (3, 4)),
- )
- else:
- dst_value = [
- _SelectableInt(value=0, bits=1),
- _SelectableInt(value=0, bits=1),
- ]
- dst_span = ["{0}", "{0}"]
- table = (
- (spec, spec_span, (0, 1)),
- (value, span, (0, 1, 2, 3, 4)),
- )
-
- for (src_value, src_span, sel) in table:
- for idx in sel:
- dst_value.append(src_value[idx])
- dst_span.append(src_span[idx])
-
- value = _selectconcat(dst_value)
- span = tuple(dst_span)
+class CR3Operand(RegisterOperand):
+ pass
- return (value, span)
- return super().spec(insn=insn, record=record, merge=merge)
+class CR5Operand(RegisterOperand):
+ def sv_spec_enter(self, value, span):
+ value = _SelectableInt(value=(value.value >> 2), bits=3)
+ return (value, span)
- def disassemble(self, insn, record, verbose=False, indent=""):
- yield from super().disassemble(prefix="cr",
- insn=insn, record=record, verbose=verbose, indent=indent)
+ def sv_spec_leave(self, value, span, origin_value, origin_span):
+ value = _selectconcat(value, origin_value[3:5])
+ span += origin_span
+ return (value, span)
class TargetAddrOperand(RegisterOperand):
yield f"{indent}{indent}{indent}{int(value):0{value.bits}b}00"
yield f"{indent}{indent}{indent}{', '.join(span + ('{0}', '{0}'))}"
else:
- yield hex(int(_selectconcat(value,
- _SelectableInt(value=0b00, bits=2))))
+ yield hex(_selectconcat(value,
+ _SelectableInt(value=0b00, bits=2)).to_signed_int())
class TargetAddrOperandLI(TargetAddrOperand):
verbosity=verbosity, indent=indent)
-class DOperandDX(DynamicOperand):
+class DOperandDX(SignedOperand):
def span(self, record):
operands = map(DynamicOperand, ("d0", "d1", "d2"))
spans = map(lambda operand: operand.span(record=record), operands)
yield f"{indent}{indent}{indent}{int(value):0{value.bits}b}"
yield f"{indent}{indent}{indent}{', '.join(span)}"
else:
- yield str(int(value))
+ yield str(value.to_signed_int())
class Operands(tuple):
"SVxd": NonZeroOperand,
"SVyd": NonZeroOperand,
"SVzd": NonZeroOperand,
+ "BD": SignedOperand,
+ "D": SignedOperand,
+ "DQ": SignedOperand,
+ "DS": SignedOperand,
+ "SI": SignedOperand,
+ "IB": SignedOperand,
+ "LI": SignedOperand,
+ "SIM": SignedOperand,
+ "SVD": SignedOperand,
+ "SVDS": SignedOperand,
}
operands = []
if immediate is not None:
operands.append(ImmediateOperand(name=immediate))
- if insn in custom_insns and operand in custom_insns[insn]:
- dynamic_cls = custom_insns[insn][operand]
if operand in custom_fields:
dynamic_cls = custom_fields[operand]
+ if insn in custom_insns and operand in custom_insns[insn]:
+ dynamic_cls = custom_insns[insn][operand]
if operand in _RegType.__members__:
regtype = _RegType[operand]
dynamic_cls = GPROperand
elif regtype is _RegType.FPR:
dynamic_cls = FPROperand
+ if regtype is _RegType.CR_BIT: # 5-bit
+ dynamic_cls = CR5Operand
+ if regtype is _RegType.CR_REG: # actually CR Field, 3-bit
+ dynamic_cls = CR3Operand
operand = dynamic_cls(name=operand)
operands.append(operand)
def __lt__(self, other):
if not isinstance(other, Record):
return NotImplemented
- return (self.opcode < other.opcode)
-
- @cached_property
- def opcode(self):
- value = ([0] * 32)
- mask = ([0] * 32)
+ return (min(self.opcodes) < min(other.opcodes))
- if self.section.opcode:
- for (src, dst) in enumerate(reversed(BitSel((0, 5)))):
- value[dst] = ((self.section.opcode.value & (1 << src)) != 0)
- mask[dst] = ((self.section.opcode.mask & (1 << src)) != 0)
-
- for (src, dst) in enumerate(reversed(self.section.bitsel)):
- value[dst] = ((self.ppc.opcode.value & (1 << src)) != 0)
- mask[dst] = ((self.ppc.opcode.mask & (1 << src)) != 0)
+ @property
+ def opcodes(self):
+ def opcode(ppc):
+ value = ([0] * 32)
+ mask = ([0] * 32)
- for operand in self.mdwn.operands.static:
- for (src, dst) in enumerate(reversed(operand.span(record=self))):
- value[dst] = ((operand.value & (1 << src)) != 0)
- mask[dst] = True
+ PO = self.section.opcode
+ if PO is not None:
+ for (src, dst) in enumerate(reversed(BitSel((0, 5)))):
+ value[dst] = int((PO.value & (1 << src)) != 0)
+ mask[dst] = int((PO.mask & (1 << src)) != 0)
- for operand in self.mdwn.operands.dynamic:
- for dst in operand.span(record=self):
- value[dst] = False
- mask[dst] = False
+ XO = ppc.opcode
+ for (src, dst) in enumerate(reversed(self.section.bitsel)):
+ value[dst] = int((XO.value & (1 << src)) != 0)
+ mask[dst] = int((XO.mask & (1 << src)) != 0)
- def onebit(bit):
- return _SelectableInt(value=int(bit), bits=1)
+ for operand in self.mdwn.operands.static:
+ for (src, dst) in enumerate(reversed(operand.span(record=self))):
+ value[dst] = int((operand.value & (1 << src)) != 0)
+ mask[dst] = 1
- value = _selectconcat(*map(onebit, value))
- mask = _selectconcat(*map(onebit, mask))
+ value = Opcode.Value(int(("".join(map(str, value))), 2))
+ mask = Opcode.Mask(int(("".join(map(str, mask))), 2))
- value = int(value)
- mask = int(mask)
+ return Opcode(value=value, mask=mask)
- return Opcode(value=value, mask=mask)
+ return tuple(sorted(map(opcode, self.ppc)))
- def match(self, opcode):
- value = self.opcode.value
- mask = self.opcode.mask
- return ((value & mask) == (opcode & mask))
+ def match(self, key):
+ for opcode in self.opcodes:
+ if ((opcode.value & opcode.mask) ==
+ (key & opcode.mask)):
+ return True
+ return False
@property
def function(self):
def cr_in(self):
return self.ppc.cr_in
+ @property
+ def cr_in2(self):
+ return self.ppc.cr_in2
+
@property
def cr_out(self):
return self.ppc.cr_out
def __hash__(self):
return hash(int(self))
+ def __getitem__(self, key):
+ return self.storage.__getitem__(key)
+
+ def __setitem__(self, key, value):
+ return self.storage.__setitem__(key, value)
+
+ def bytes(self, byteorder="little"):
+ nr_bytes = (self.storage.bits // 8)
+ return int(self).to_bytes(nr_bytes, byteorder=byteorder)
+
def record(self, db):
record = db[self]
if record is None:
bits.append(bit)
return "".join(map(str, bits))
- def opcode(self, db):
- record = self.record(db=db)
- return f"0x{record.opcode.value:08x}"
-
- def mask(self, db):
- record = self.record(db=db)
- return f"0x{record.opcode.mask:08x}"
-
def disassemble(self, db,
byteorder="little",
verbosity=Verbosity.NORMAL):
indent = (" " * 4)
binary = self.binary
spec = self.spec(db=db, prefix="")
- opcode = self.opcode(db=db)
- mask = self.mask(db=db)
yield f"{indent}spec"
yield f"{indent}{indent}{spec}"
yield f"{indent}pcode"
yield f"{indent}{indent}[8:16] {binary[8:16]}"
yield f"{indent}{indent}[16:24] {binary[16:24]}"
yield f"{indent}{indent}[24:32] {binary[24:32]}"
- yield f"{indent}opcode"
- yield f"{indent}{indent}{opcode}"
- yield f"{indent}mask"
- yield f"{indent}{indent}{mask}"
+ yield f"{indent}opcodes"
+ for opcode in record.opcodes:
+ yield f"{indent}{indent}{opcode!r}"
for operand in record.mdwn.operands:
yield from operand.disassemble(insn=self, record=record,
verbosity=verbosity, indent=indent)
(prefix, suffix) = map(transform, (prefix, suffix))
value = _selectconcat(prefix, suffix)
- return super().integer(value=value)
+ return super().integer(bits=64, value=value)
class Mode(_Mapping):
_: _Field = range(0, 5)
- sel: _Field = range(0, 2)
-
-
-class NormalMode(Mode):
- class simple(Mode):
- """simple mode"""
- dz: Mode[3]
- sz: Mode[4]
-
- class smr(Mode):
- """scalar reduce mode (mapreduce), SUBVL=1"""
- RG: Mode[4]
-
- class pmr(Mode):
- """parallel reduce mode (mapreduce), SUBVL=1"""
- pass
-
- class svmr(Mode):
- """subvector reduce mode, SUBVL>1"""
- SVM: Mode[3]
-
- class pu(Mode):
- """Pack/Unpack mode, SUBVL>1"""
- SVM: Mode[3]
-
- class ffrc1(Mode):
- """Rc=1: ffirst CR sel"""
- inv: Mode[2]
- CRbit: Mode[3, 4]
-
- class ffrc0(Mode):
- """Rc=0: ffirst z/nonz"""
- inv: Mode[2]
- VLi: Mode[3]
- RC1: Mode[4]
-
- class sat(Mode):
- """sat mode: N=0/1 u/s, SUBVL=1"""
- N: Mode[2]
- dz: Mode[3]
- sz: Mode[4]
-
- class satx(Mode):
- """sat mode: N=0/1 u/s, SUBVL>1"""
- N: Mode[2]
- zz: Mode[3]
- dz: Mode[3]
- sz: Mode[3]
-
- class satpu(Mode):
- """Pack/Unpack sat mode: N=0/1 u/s, SUBVL>1"""
- N: Mode[2]
- zz: Mode[3]
- dz: Mode[3]
- sz: Mode[3]
-
- class prrc1(Mode):
- """Rc=1: pred-result CR sel"""
- inv: Mode[2]
- CRbit: Mode[3, 4]
-
- class prrc0(Mode):
- """Rc=0: pred-result z/nonz"""
- inv: Mode[2]
- zz: Mode[3]
- RC1: Mode[4]
- dz: Mode[3]
- sz: Mode[3]
-
- simple: simple
- smr: smr
- pmr: pmr
- svmr: svmr
- pu: pu
- ffrc1: ffrc1
- ffrc0: ffrc0
- sat: sat
- satx: satx
- satpu: satpu
- prrc1: prrc1
- prrc0: prrc0
-
-
-class LDSTImmMode(Mode):
- class simple(Mode):
- """simple mode"""
- zz: Mode[3]
- els: Mode[4]
- dz: Mode[3]
- sz: Mode[3]
-
- class spu(Mode):
- """Structured Pack/Unpack"""
- zz: Mode[3]
- els: Mode[4]
- dz: Mode[3]
- sz: Mode[3]
-
- class ffrc1(Mode):
- """Rc=1: ffirst CR sel"""
- inv: Mode[2]
- CRbit: Mode[3, 4]
-
- class ffrc0(Mode):
- """Rc=0: ffirst z/nonz"""
- inv: Mode[2]
- els: Mode[3]
- RC1: Mode[4]
-
- class sat(Mode):
- """sat mode: N=0/1 u/s"""
- N: Mode[2]
- zz: Mode[3]
- els: Mode[4]
- dz: Mode[3]
- sz: Mode[3]
-
- class prrc1(Mode):
- """Rc=1: pred-result CR sel"""
- inv: Mode[2]
- CRbit: Mode[3, 4]
-
- class prrc0(Mode):
- """Rc=0: pred-result z/nonz"""
- inv: Mode[2]
- els: Mode[3]
- RC1: Mode[4]
-
- simple: simple
- spu: spu
- ffrc1: ffrc1
- ffrc0: ffrc0
- sat: sat
- prrc1: prrc1
- prrc0: prrc0
-
-
-class LDSTIdxMode(Mode):
- class simple(Mode):
- """simple mode"""
- SEA: Mode[2]
- sz: Mode[3]
- dz: Mode[3]
-
- class stride(Mode):
- """strided (scalar only source)"""
- SEA: Mode[2]
- dz: Mode[3]
- sz: Mode[4]
-
- class sat(Mode):
- """sat mode: N=0/1 u/s"""
- N: Mode[2]
- dz: Mode[3]
- sz: Mode[4]
-
- class prrc1(Mode):
- """Rc=1: pred-result CR sel"""
- inv: Mode[2]
- CRbit: Mode[3, 4]
-
- class prrc0(Mode):
- """Rc=0: pred-result z/nonz"""
- inv: Mode[2]
- zz: Mode[3]
- RC1: Mode[4]
- dz: Mode[3]
- sz: Mode[3]
-
- simple: simple
- stride: stride
- sat: sat
- prrc1: prrc1
- prrc0: prrc0
class Extra(_Mapping):
self[key].assign(value)
-class RM(_Mapping):
- class Mode(Mode):
- normal: NormalMode
- ldst_imm: LDSTImmMode
- ldst_idx: LDSTIdxMode
-
+class BaseRM(_Mapping):
_: _Field = range(24)
mmode: _Field = (0,)
mask: _Field = range(1, 4)
subvl: _Field = range(8, 10)
mode: Mode.remap(range(19, 24))
smask: _Field = range(16, 19)
-
extra: Extra.remap(range(10, 19))
extra2: Extra2.remap(range(10, 19))
extra3: Extra3.remap(range(10, 19))
+ def specifiers(self, record):
+ subvl = int(self.subvl)
+ if subvl > 0:
+ yield {
+ 1: "vec2",
+ 2: "vec3",
+ 3: "vec4",
+ }[subvl]
+
+ def disassemble(self, verbosity=Verbosity.NORMAL):
+ if verbosity >= Verbosity.VERBOSE:
+ indent = (" " * 4)
+ for (name, value, members) in self.traverse(path="RM"):
+ yield f"{name}"
+ yield f"{indent}{int(value):0{value.bits}b}"
+ yield f"{indent}{', '.join(map(str, members))}"
+
+
+class NormalLDSTBaseRM(BaseRM):
+ def specifiers(self, record):
+ widths = {
+ 0b11: "8",
+ 0b10: "16",
+ 0b01: "32",
+ }
+ predicates = {
+ # integer
+ (0, 0b001): "1<<r3",
+ (0, 0b010): "r3",
+ (0, 0b011): "~r3",
+ (0, 0b100): "r10",
+ (0, 0b101): "~r10",
+ (0, 0b110): "r30",
+ (0, 0b111): "~r30",
+ # CRs
+ (1, 0b000): "lt",
+ (1, 0b001): "ge",
+ (1, 0b010): "gt",
+ (1, 0b011): "le",
+ (1, 0b100): "eq",
+ (1, 0b101): "ne",
+ (1, 0b110): "so",
+ (1, 0b111): "ns",
+ }
+
+ mmode = int(self.mmode)
+ mask = int(self.mask)
+ if record.svp64.ptype is _SVPtype.P2:
+ (smask, dmask) = (int(self.smask), mask)
+ else:
+ (smask, dmask) = (mask, mask)
+ if all((smask, dmask)) and (smask == dmask):
+ yield f"m={predicates[(mmode, smask)]}"
+ else:
+ sw = predicates.get((mmode, smask))
+ dw = predicates.get((mmode, dmask))
+ if sw:
+ yield f"sm={sw}"
+ if dw:
+ yield f"dm={dw}"
+
+ dw = int(self.elwidth)
+ sw = int(self.ewsrc)
+ if all((dw, sw)) and (dw == sw):
+ yield f"w={widths[dw]}"
+ else:
+ if dw != 0b00:
+ yield f"dw={widths[dw]}"
+ if sw != 0b00:
+ yield f"sw={widths[sw]}"
+
+ yield from super().specifiers(record=record)
+
+
+class NormalBaseRM(NormalLDSTBaseRM):
+ pass
+
+
+class NormalSimpleRM(NormalBaseRM):
+ """normal: simple mode"""
+ dz: BaseRM.mode[3]
+ sz: BaseRM.mode[4]
+
+ def specifiers(self, record):
+ if self.dz:
+ yield f"dz"
+ if self.sz:
+ yield f"sz"
+ yield from super().specifiers(record=record)
+
+
+class NormalScalarReduceRM(NormalBaseRM):
+ """normal: scalar reduce mode (mapreduce), SUBVL=1"""
+ RG: BaseRM.mode[4]
+
+ def specifiers(self, record):
+ if self.RG:
+ yield "mrr"
+
+ yield from super().specifiers(record=record)
+
+
+class NormalReservedRM(NormalBaseRM):
+ """normal: reserved"""
+ pass
+
+
+class NormalFailFirstRc1RM(NormalBaseRM):
+ """normal: Rc=1: ffirst CR sel"""
+ inv: BaseRM.mode[2]
+ CR: BaseRM.mode[3, 4]
+
+
+class NormalFailFirstRc0RM(NormalBaseRM):
+ """normal: Rc=0: ffirst z/nonz"""
+ inv: BaseRM.mode[2]
+ VLi: BaseRM.mode[3]
+ RC1: BaseRM.mode[4]
+
+ def specifiers(self, record):
+ if self.RC1:
+ inv = "~" if self.inv else ""
+ yield f"ff={inv}RC1"
+
+ yield from super().specifiers(record=record)
+
+
+class NormalSaturationRM(NormalBaseRM):
+ """normal: sat mode: N=0/1 u/s, SUBVL=1"""
+ N: BaseRM.mode[2]
+ dz: BaseRM.mode[3]
+ sz: BaseRM.mode[4]
+
+ def specifiers(self, record):
+ if self.dz:
+ yield f"dz"
+ if self.sz:
+ yield f"sz"
+ if self.N:
+ yield "sats"
+ else:
+ yield "satu"
+
+ yield from super().specifiers(record=record)
+
+
+class NormalPredResultRc1RM(NormalBaseRM):
+ """normal: Rc=1: pred-result CR sel"""
+ inv: BaseRM.mode[2]
+ CR: BaseRM.mode[3, 4]
+
+
+class NormalPredResultRc0RM(NormalBaseRM):
+ """normal: Rc=0: pred-result z/nonz"""
+ inv: BaseRM.mode[2]
+ zz: BaseRM.mode[3]
+ RC1: BaseRM.mode[4]
+ dz: BaseRM.mode[3]
+ sz: BaseRM.mode[3]
+
+ def specifiers(self, record):
+ if self.zz:
+ yield f"zz"
+ if self.RC1:
+ inv = "~" if self.inv else ""
+ yield f"pr={inv}RC1"
+
+ yield from super().specifiers(record=record)
+
+
+class NormalRM(NormalBaseRM):
+ simple: NormalSimpleRM
+ smr: NormalScalarReduceRM
+ reserved: NormalReservedRM
+ ffrc1: NormalFailFirstRc1RM
+ ffrc0: NormalFailFirstRc0RM
+ sat: NormalSaturationRM
+ prrc1: NormalPredResultRc1RM
+ prrc0: NormalPredResultRc0RM
+
+
+class LDSTImmBaseRM(NormalLDSTBaseRM):
+ pass
+
+
+class LDSTImmSimpleRM(LDSTImmBaseRM):
+ """ld/st immediate: simple mode"""
+ zz: BaseRM.mode[3]
+ els: BaseRM.mode[4]
+ dz: BaseRM.mode[3]
+ sz: BaseRM.mode[3]
+
+ def specifiers(self, record):
+ if self.zz:
+ yield f"zz"
+
+ yield from super().specifiers(record=record)
+
+
+class LDSTImmReservedRM(LDSTImmBaseRM):
+ """ld/st immediate: reserved"""
+ pass
+
+
+class LDSTImmFailFirstRc1RM(LDSTImmBaseRM):
+ """ld/st immediate: Rc=1: ffirst CR sel"""
+ inv: BaseRM.mode[2]
+ CR: BaseRM.mode[3, 4]
+
+
+class LDSTImmFailFirstRc0RM(LDSTImmBaseRM):
+ """ld/st immediate: Rc=0: ffirst z/nonz"""
+ inv: BaseRM.mode[2]
+ els: BaseRM.mode[3]
+ RC1: BaseRM.mode[4]
+
+ def specifiers(self, record):
+ if self.RC1:
+ inv = "~" if self.inv else ""
+ yield f"ff={inv}RC1"
+
+ yield from super().specifiers(record=record)
+
+class LDSTImmSaturationRM(LDSTImmBaseRM):
+ """ld/st immediate: sat mode: N=0/1 u/s"""
+ N: BaseRM.mode[2]
+ zz: BaseRM.mode[3]
+ els: BaseRM.mode[4]
+ dz: BaseRM.mode[3]
+ sz: BaseRM.mode[3]
+
+ def specifiers(self, record):
+ if self.zz:
+ yield f"zz"
+ if self.N:
+ yield "sats"
+ else:
+ yield "satu"
+
+ yield from super().specifiers(record=record)
+
+
+class LDSTImmPredResultRc1RM(LDSTImmBaseRM):
+ """ld/st immediate: Rc=1: pred-result CR sel"""
+ inv: BaseRM.mode[2]
+ CR: BaseRM.mode[3, 4]
+
+
+class LDSTImmPredResultRc0RM(LDSTImmBaseRM):
+ """ld/st immediate: Rc=0: pred-result z/nonz"""
+ inv: BaseRM.mode[2]
+ els: BaseRM.mode[3]
+ RC1: BaseRM.mode[4]
+
+ def specifiers(self, record):
+ if self.RC1:
+ inv = "~" if self.inv else ""
+ yield f"pr={inv}RC1"
+
+ yield from super().specifiers(record=record)
+
+class LDSTImmRM(LDSTImmBaseRM):
+ simple: LDSTImmSimpleRM
+ reserved: LDSTImmReservedRM
+ ffrc1: LDSTImmFailFirstRc1RM
+ ffrc0: LDSTImmFailFirstRc0RM
+ sat: LDSTImmSaturationRM
+ prrc1: LDSTImmPredResultRc1RM
+ prrc0: LDSTImmPredResultRc0RM
+
+
+class LDSTIdxBaseRM(NormalLDSTBaseRM):
+ pass
+
+
+class LDSTIdxSimpleRM(LDSTIdxBaseRM):
+ """ld/st index: simple mode"""
+ SEA: BaseRM.mode[2]
+ sz: BaseRM.mode[3]
+ dz: BaseRM.mode[3]
+
+ def specifiers(self, record):
+ if self.dz:
+ yield f"dz"
+ if self.sz:
+ yield f"sz"
+
+ yield from super().specifiers(record=record)
+
+
+class LDSTIdxStrideRM(LDSTIdxBaseRM):
+ """ld/st index: strided (scalar only source)"""
+ SEA: BaseRM.mode[2]
+ dz: BaseRM.mode[3]
+ sz: BaseRM.mode[4]
+
+ def specifiers(self, record):
+ if self.dz:
+ yield f"dz"
+ if self.sz:
+ yield f"sz"
+
+ yield from super().specifiers(record=record)
+
+
+class LDSTIdxSaturationRM(LDSTIdxBaseRM):
+ """ld/st index: sat mode: N=0/1 u/s"""
+ N: BaseRM.mode[2]
+ dz: BaseRM.mode[3]
+ sz: BaseRM.mode[4]
+
+ def specifiers(self, record):
+ if self.dz:
+ yield f"dz"
+ if self.sz:
+ yield f"sz"
+ if self.N:
+ yield "sats"
+ else:
+ yield "satu"
+
+ yield from super().specifiers(record=record)
+
+
+class LDSTIdxPredResultRc1RM(LDSTIdxBaseRM):
+ """ld/st index: Rc=1: pred-result CR sel"""
+ inv: BaseRM.mode[2]
+ CR: BaseRM.mode[3, 4]
+
+
+class LDSTIdxPredResultRc0RM(LDSTIdxBaseRM):
+ """ld/st index: Rc=0: pred-result z/nonz"""
+ inv: BaseRM.mode[2]
+ zz: BaseRM.mode[3]
+ RC1: BaseRM.mode[4]
+ dz: BaseRM.mode[3]
+ sz: BaseRM.mode[3]
+
+ def specifiers(self, record):
+ if self.zz:
+ yield f"zz"
+ if self.RC1:
+ inv = "~" if self.inv else ""
+ yield f"pr={inv}RC1"
+
+ yield from super().specifiers(record=record)
+
+
+class LDSTIdxRM(LDSTIdxBaseRM):
+ simple: LDSTIdxSimpleRM
+ stride: LDSTIdxStrideRM
+ sat: LDSTIdxSaturationRM
+ prrc1: LDSTIdxPredResultRc1RM
+ prrc0: LDSTIdxPredResultRc0RM
+
+
+class CROpBaseRM(BaseRM):
+ pass
+
+
+class CROpSimpleRM(CROpBaseRM):
+ """cr_op: simple mode"""
+ sz: BaseRM[6]
+ SNZ: BaseRM[7]
+ RG: BaseRM[20]
+ dz: BaseRM[22]
+
+ def specifiers(self, record):
+ if self.dz:
+ yield f"dz"
+ if self.sz:
+ yield f"sz"
+ if self.RG:
+ yield "mrr"
+
+ yield from super().specifiers(record=record)
+
+
+class CROpScalarReduceRM(CROpBaseRM):
+ """cr_op: scalar reduce mode (mapreduce), SUBVL=1"""
+ sz: BaseRM[6]
+ SNZ: BaseRM[7]
+ RG: BaseRM[20]
+
+ def specifiers(self, record):
+ if self.sz:
+ yield f"sz"
+ if self.RG:
+ yield "mrr"
+
+ yield from super().specifiers(record=record)
+
+
+class CROpReservedRM(CROpBaseRM):
+ """cr_op: reserved"""
+ zz: BaseRM[6]
+ SNZ: BaseRM[7]
+ RG: BaseRM[20]
+ dz: BaseRM[6]
+ sz: BaseRM[6]
+
+ def specifiers(self, record):
+ if self.zz:
+ yield f"zz"
+ if self.RG:
+ yield "mrr"
+
+ yield from super().specifiers(record=record)
+
+
+class CROpFailFirst3RM(CROpBaseRM):
+ """cr_op: ffirst 3-bit mode"""
+ zz: BaseRM[6]
+ SNZ: BaseRM[7]
+ VLI: BaseRM[20]
+ inv: BaseRM[21]
+ CR: BaseRM[22, 23]
+ dz: BaseRM[6]
+ sz: BaseRM[6]
+
+ def specifiers(self, record):
+ if self.zz:
+ yield f"zz"
+ yield from super().specifiers(record=record)
+
+
+class CROpFailFirst5RM(CROpBaseRM):
+ """cr_op: ffirst 5-bit mode"""
+ sz: BaseRM[6]
+ SNZ: BaseRM[7]
+ VLI: BaseRM[20]
+ inv: BaseRM[21]
+ dz: BaseRM[22]
+
+ def specifiers(self, record):
+ if self.dz:
+ yield f"dz"
+ if self.sz:
+ yield f"sz"
+ yield from super().specifiers(record=record)
+
+
+class CROpRM(CROpBaseRM):
+ simple: CROpSimpleRM
+ smr: CROpScalarReduceRM
+ reserved: CROpReservedRM
+ ff3: CROpFailFirst3RM
+ ff5: CROpFailFirst5RM
+
+
+class BranchBaseRM(BaseRM):
+ ALL: BaseRM[4]
+ SNZ: BaseRM[5]
+ SL: BaseRM[17]
+ SLu: BaseRM[18]
+ LRu: BaseRM[22]
+ sz: BaseRM[23]
+
+
+class BranchSimpleRM(BranchBaseRM):
+ """branch: simple mode"""
+ pass
+
+
+class BranchVLSRM(BranchBaseRM):
+ """branch: VLSET mode"""
+ VSb: BaseRM[7]
+ VLI: BaseRM[21]
+
+
+class BranchCTRRM(BranchBaseRM):
+ """branch: CTR-test mode"""
+ CTi: BaseRM[6]
+
+
+class BranchCTRVLSRM(BranchVLSRM, BranchCTRRM):
+ """branch: CTR-test+VLSET mode"""
+ pass
+
+
+class BranchRM(BranchBaseRM):
+ simple: BranchSimpleRM
+ vls: BranchVLSRM
+ ctr: BranchCTRRM
+ ctrvls: BranchCTRVLSRM
+
+
+class RM(BaseRM):
+ normal: NormalRM
+ ldst_imm: LDSTImmRM
+ ldst_idx: LDSTIdxRM
+ cr_op: CROpRM
+
+ def select(self, record, Rc):
+ rm = self
+
+ # the idea behind these tables is that they are now literally
+ # in identical format to insndb.csv and minor_xx.csv and can
+ # be done precisely as that. the only thing to watch out for
+ # is the insertion of Rc=1 as a "mask/value" bit and likewise
+ # regtype detection (3-bit BF/BFA, 5-bit BA/BB/BT) also inserted
+ # as the LSB.
+ table = None
+ if record.svp64.mode is _SVMode.NORMAL:
+ # concatenate mode 5-bit with Rc (LSB) then do a mask/map search
+ # mode Rc mask Rc member
+ table = (
+ (0b000000, 0b111000, "simple"), # simple (no Rc)
+ (0b001000, 0b111000, "smr"), # mapreduce (no Rc)
+ (0b010000, 0b110001, "ffrc0"), # ffirst, Rc=0
+ (0b010001, 0b110001, "ffrc1"), # ffirst, Rc=1
+ (0b100000, 0b110000, "sat"), # saturation (no Rc)
+ (0b110000, 0b110001, "prrc0"), # predicate, Rc=0
+ (0b110001, 0b110001, "prrc1"), # predicate, Rc=1
+ )
+ rm = rm.normal
+ search = ((int(rm.mode) << 1) | Rc)
+
+ elif record.svp64.mode is _SVMode.LDST_IMM:
+ # concatenate mode 5-bit with Rc (LSB) then do a mask/map search
+ # mode Rc mask Rc member
+ # ironically/coincidentally this table is identical to NORMAL
+ # mode except reserved in place of smr
+ table = (
+ (0b000000, 0b111000, "simple"), # simple (no Rc)
+ (0b001000, 0b111000, "reserved"), # rsvd (no Rc)
+ (0b010000, 0b110001, "ffrc0"), # ffirst, Rc=0
+ (0b010001, 0b110001, "ffrc1"), # ffirst, Rc=1
+ (0b100000, 0b110000, "sat"), # saturation (no Rc)
+ (0b110000, 0b110001, "prrc0"), # predicate, Rc=0
+ (0b110001, 0b110001, "prrc1"), # predicate, Rc=1
+ )
+ rm = rm.ldst_imm
+ search = ((int(rm.mode) << 1) | Rc)
+
+ elif record.svp64.mode is _SVMode.LDST_IDX:
+ # concatenate mode 5-bit with Rc (LSB) then do a mask/map search
+ # mode Rc mask Rc member
+ table = (
+ (0b000000, 0b111000, "simple"), # simple (no Rc)
+ (0b010000, 0b110000, "stride"), # strided, (no Rc)
+ (0b100000, 0b110000, "sat"), # saturation (no Rc)
+ (0b110000, 0b110001, "prrc0"), # predicate, Rc=0
+ (0b110001, 0b110001, "prrc1"), # predicate, Rc=1
+ )
+ rm = rm.ldst_idx
+ search = ((int(rm.mode) << 1) | Rc)
+
+ elif record.svp64.mode is _SVMode.CROP:
+ # concatenate mode 5-bit with regtype (LSB) then do mask/map search
+ # mode 3b mask 3b member
+ table = (
+ (0b000000, 0b111000, "simple"), # simple
+ (0b001000, 0b111000, "smr"), # mapreduce
+ (0b100000, 0b100000, "ff5"), # failfirst, 5-bit CR
+ (0b100001, 0b100001, "ff3"), # failfirst, 3-bit CR
+ )
+ # determine CR type, 5-bit (BA/BB/BT) or 3-bit Field (BF/BFA)
+ regtype = None
+ for idx in range(0, 4):
+ for entry in record.svp64.extra[idx]:
+ if entry.regtype is _SVExtraRegType.DST:
+ if regtype is not None:
+ raise ValueError(record.svp64)
+ regtype = _RegType(entry.reg)
+ if regtype is _RegType.CR_REG:
+ regtype = 0 # 5-bit
+ elif regtype is _RegType.CR_BIT:
+ regtype = 1 # 3-bit
+ else:
+ raise ValueError(record.svp64)
+ # finally provide info for search
+ rm = rm.cr_op
+ search = ((int(rm.mode) << 1) | (regtype or 0))
+
+ elif record.svp64.mode is _SVMode.BRANCH:
+ # just mode 5-bit. could be reduced down to 2, oh well.
+ # mode mask action(getattr)
+ table = [(0b00000, 0b11000, "simple"), # simple
+ (0b01000, 0b11000, "vls"), # VLset
+ (0b10000, 0b11000, "ctr"), # CTR mode
+ (0b11000, 0b11000, "ctrvls"), # CTR+VLset mode
+ ]
+ # slightly weird: doesn't have a 5-bit "mode" field like others
+ search = int(rm[19:23])
+
+ # look up in table
+ if table is not None:
+ for (value, mask, member) in table:
+ if ((value & search) == (mask & search)):
+ rm = getattr(rm, member)
+ break
+
+ if rm.__class__ is self.__class__:
+ raise ValueError(self)
+
+ return rm
+
class SVP64Instruction(PrefixedInstruction):
"""SVP64 instruction: https://libre-soc.org/openpower/sv/svp64/"""
prefix: Prefix
+ def record(self, db):
+ record = db[self.suffix]
+ if record is None:
+ raise KeyError(self)
+ return record
+
@property
def binary(self):
bits = []
bits.append(bit)
return "".join(map(str, bits))
- def opcode(self, db):
- return self.suffix.opcode(db=db)
-
- def mask(self, db):
- return self.suffix.mask(db=db)
-
- def mode(self, db):
- record = self.record(db=db)
-
- Rc = False
- if record.mdwn.operands["Rc"] is not None:
- Rc = bool(self[record.fields["Rc"]])
-
- record = self.record(db=db)
- subvl = self.prefix.rm.subvl
- mode = self.prefix.rm.mode
- sel = mode.sel
-
- if record.svp64.mode is _SVMode.NORMAL:
- mode = mode.normal
- if sel == 0b00:
- if mode[2] == 0b0:
- mode = mode.simple
- else:
- if subvl == 0b00:
- if mode[3] == 0b0:
- mode = mode.smr
- else:
- mode = mode.pmr
- else:
- if mode[4] == 0b0:
- mode = mode.svmr
- else:
- mode = mode.pu
- elif sel == 0b01:
- if Rc:
- mode = mode.ffrc1
- else:
- mode = mode.ffrc0
- elif sel == 0b10:
- if subvl == 0b00:
- mode = mode.sat
- else:
- if mode[4]:
- mode = mode.satx
- else:
- mode = mode.satpu
- elif sel == 0b11:
- if Rc:
- mode = mode.prrc1
- else:
- mode = mode.prrc0
- elif record.svp64.mode is _SVMode.LDST_IMM:
- mode = mode.ldst_imm
- if sel == 0b00:
- if mode[2] == 0b0:
- mode = mode.simple
- else:
- mode = mode.spu
- elif sel == 0b01:
- if Rc:
- mode = mode.ffrc1
- else:
- mode = mode.ffrc0
- elif sel == 0b10:
- mode = mode.sat
- elif sel == 0b11:
- if Rc:
- mode = mode.prrc1
- else:
- mode = mode.prrc0
- elif record.svp64.mode is _SVMode.LDST_IMM:
- mode = mode.ldst_idx
- if mode.sel == 0b00:
- mode = mode.simple
- elif mode.sel == 0b01:
- mode = mode.stride
- elif mode.sel == 0b10:
- mode = mode.sat
- elif mode.sel == 0b11:
- if Rc:
- mode = mode.prrc1
- else:
- mode = mode.prrc0
-
- modes = {
- NormalMode.simple: "normal: simple",
- NormalMode.smr: "normal: smr",
- NormalMode.pmr: "normal: pmr",
- NormalMode.svmr: "normal: svmr",
- NormalMode.pu: "normal: pu",
- NormalMode.ffrc1: "normal: ffrc1",
- NormalMode.ffrc0: "normal: ffrc0",
- NormalMode.sat: "normal: sat",
- NormalMode.satx: "normal: satx",
- NormalMode.satpu: "normal: satpu",
- NormalMode.prrc1: "normal: prrc1",
- NormalMode.prrc0: "normal: prrc0",
- LDSTImmMode.simple: "ld/st imm: simple",
- LDSTImmMode.spu: "ld/st imm: spu",
- LDSTImmMode.ffrc1: "ld/st imm: ffrc1",
- LDSTImmMode.ffrc0: "ld/st imm: ffrc0",
- LDSTImmMode.sat: "ld/st imm: sat",
- LDSTImmMode.prrc1: "ld/st imm: prrc1",
- LDSTImmMode.prrc0: "ld/st imm: prrc0",
- LDSTIdxMode.simple: "ld/st idx simple",
- LDSTIdxMode.stride: "ld/st idx stride",
- LDSTIdxMode.sat: "ld/st idx sat",
- LDSTIdxMode.prrc1: "ld/st idx prrc1",
- LDSTIdxMode.prrc0: "ld/st idx prrc0",
- }
- for (cls, desc) in modes.items():
- if isinstance(mode, cls):
- return (mode, desc)
-
- if record.svp64.mode is _SVMode.BRANCH:
- return (self.prefix.rm.mode, "branch")
-
- raise ValueError(self)
-
def disassemble(self, db,
byteorder="little",
verbosity=Verbosity.NORMAL):
blob = " ".join(map(lambda byte: f"{byte:02x}", blob))
return f"{blob} "
+ record = self.record(db=db)
blob_prefix = blob(int(self.prefix))
blob_suffix = blob(int(self.suffix))
- record = db[self]
if record is None or record.svp64 is None:
yield f"{blob_prefix}.long 0x{int(self.prefix):08x}"
yield f"{blob_suffix}.long 0x{int(self.suffix):08x}"
return
+ name = f"sv.{record.name}"
+
+ Rc = False
+ if record.mdwn.operands["Rc"] is not None:
+ Rc = bool(record.mdwn.operands["Rc"].value)
+ rm = self.prefix.rm.select(record=record, Rc=Rc)
+
+ specifiers = tuple(rm.specifiers(record=record))
+ if specifiers:
+ specifiers = "/".join(specifiers)
+ specifiers = f"/{specifiers}"
+ else:
+ specifiers = ""
+
operands = tuple(map(_operator.itemgetter(1),
self.dynamic_operands(db=db, verbosity=verbosity)))
if operands:
- yield f"{blob_prefix}sv.{record.name} {','.join(operands)}"
+ operands = f" {','.join(operands)}"
else:
- yield f"{blob_prefix}{record.name}"
+ operands = ""
+
+ yield f"{blob_prefix}{name}{specifiers}{operands}"
if blob_suffix:
yield f"{blob_suffix}"
- (mode, mode_desc) = self.mode(db=db)
-
if verbosity >= Verbosity.VERBOSE:
indent = (" " * 4)
binary = self.binary
spec = self.spec(db=db, prefix="sv.")
- opcode = self.opcode(db=db)
- mask = self.mask(db=db)
+
yield f"{indent}spec"
yield f"{indent}{indent}{spec}"
yield f"{indent}pcode"
yield f"{indent}{indent}[40:48] {binary[40:48]}"
yield f"{indent}{indent}[48:56] {binary[48:56]}"
yield f"{indent}{indent}[56:64] {binary[56:64]}"
- yield f"{indent}opcode"
- yield f"{indent}{indent}{opcode}"
- yield f"{indent}mask"
- yield f"{indent}{indent}{mask}"
+ yield f"{indent}opcodes"
+ for opcode in record.opcodes:
+ yield f"{indent}{indent}{opcode!r}"
for operand in record.mdwn.operands:
yield from operand.disassemble(insn=self, record=record,
verbosity=verbosity, indent=indent)
-
- yield f"{indent}mode"
- yield f"{indent}{indent}{mode_desc}"
+ yield f"{indent}RM"
+ yield f"{indent}{indent}{rm.__doc__}"
+ for line in rm.disassemble(verbosity=verbosity):
+ yield f"{indent}{indent}{line}"
yield ""
def __iter__(self):
yield from self.__db.items()
+ def __contains__(self, key):
+ return self.__db.__contains__(key)
+
def __getitem__(self, key):
return self.__db.__getitem__(key)
for insn in parse(stream, factory):
records[section][insn.comment].add(insn)
- db = dd(set)
+ sections = dd(set)
for (section, group) in records.items():
for records in group.values():
- db[section].add(PPCMultiRecord(records))
+ sections[section].add(PPCMultiRecord(records))
+
+ db = {}
+ for (section, records) in sections.items():
+ for record in records:
+ def exact_match(names):
+ for name in names:
+ if name in mdwndb:
+ yield name
+
+ def Rc_match(names):
+ for name in names:
+ if f"{name}." in mdwndb:
+ yield f"{name}."
+ yield name
+
+ def LK_match(names):
+ if "lk" not in record.flags:
+ yield from names
+ return
+
+ for name in names:
+ if f"{name}l" in mdwndb:
+ yield f"{name}l"
+ yield name
+
+ def AA_match(names):
+ if record.intop not in {_MicrOp.OP_B, _MicrOp.OP_BC}:
+ yield from names
+ return
+
+ for name in names:
+ operands = mdwndb[name].operands["AA"]
+ if ((operands is not None) and
+ (f"{name}a" in mdwndb)):
+ yield f"{name}a"
+ yield name
+
+ def reductor(names, match):
+ return match(names)
+
+ matches = (exact_match, Rc_match, LK_match, AA_match)
+
+ names = _functools.reduce(reductor, matches, record.names)
+ for name in names:
+ db[name] = (section, record)
self.__db = db
self.__mdwndb = mdwndb
return super().__init__()
+ @_functools.lru_cache(maxsize=512, typed=False)
def __getitem__(self, key):
- def exact_match(key, record):
- for name in record.names:
- if name == key:
- return True
-
- return False
-
- def Rc_match(key, record):
- if not key.endswith("."):
- return False
-
- if not record.Rc is _RCOE.RC:
- return False
-
- return exact_match(key[:-1], record)
-
- def LK_match(key, record):
- if not key.endswith("l"):
- return False
-
- if "lk" not in record.flags:
- return False
-
- return exact_match(key[:-1], record)
-
- def AA_match(key, record):
- if not key.endswith("a"):
- return False
-
- if record.intop not in {_MicrOp.OP_B, _MicrOp.OP_BC}:
- return False
-
- if self.__mdwndb[key].operands["AA"] is None:
- return False
-
- return (exact_match(key[:-1], record) or
- LK_match(key[:-1], record))
-
- for (section, records) in self.__db.items():
- for record in records:
- if exact_match(key, record):
- return (section, record)
-
- for record in records:
- if (Rc_match(key, record) or
- LK_match(key, record) or
- AA_match(key, record)):
- return (section, record)
-
- return (None, None)
+ return self.__db.get(key, (None, None))
class SVP64Database:
class Database:
def __init__(self, root):
root = _pathlib.Path(root)
-
mdwndb = MarkdownDatabase()
fieldsdb = FieldsDatabase()
ppcdb = PPCDatabase(root=root, mdwndb=mdwndb)
svp64db = SVP64Database(root=root, ppcdb=ppcdb)
db = set()
+ names = {}
+ opcodes = _collections.defaultdict(set)
+
for (name, mdwn) in mdwndb:
(section, ppc) = ppcdb[name]
if ppc is None:
section=section, ppc=ppc, svp64=svp64,
mdwn=mdwn, fields=fields)
db.add(record)
+ names[record.name] = record
+ PO = section.opcode
+ if PO is None:
+ PO = ppc[0].opcode
+ opcodes[PO.value].add(record)
- self.__db = tuple(sorted(db))
+ self.__db = db
+ self.__names = names
+ self.__opcodes = opcodes
return super().__init__()
def __getitem__(self, key):
if isinstance(key, (int, Instruction)):
key = int(key)
- for record in self:
- opcode = record.opcode
- if record.match(opcode=key):
+ XO = int(_SelectableInt(value=int(key), bits=32)[0:6])
+ for record in self.__opcodes[XO]:
+ if record.match(key=key):
return record
- return None
- elif isinstance(key, Opcode):
- for record in self:
- if record.opcode == key:
- return record
elif isinstance(key, str):
- for record in self:
- if record.name == key:
- return record
+ return self.__names[key]
+
return None
projects / openpower-isa.git / blobdiff