VLi: BaseRM.mode[3]
RC1: BaseRM.mode[4]
+ def specifiers(self, record):
+ if self.RC1:
+ inv = "~" if self.inv else ""
+ yield f"ff={inv}RC1"
+
+ yield from super().specifiers(record=record)
+
class NormalSaturationRM(NormalBaseRM):
"""normal: sat mode: N=0/1 u/s, SUBVL=1"""
def specifiers(self, record):
if self.zz:
yield f"zz"
+ if self.RC1:
+ inv = "~" if self.inv else ""
+ yield f"pr={inv}RC1"
yield from super().specifiers(record=record)
els: BaseRM.mode[3]
RC1: BaseRM.mode[4]
+ def specifiers(self, record):
+ if self.RC1:
+ inv = "~" if self.inv else ""
+ yield f"ff={inv}RC1"
+
+ yield from super().specifiers(record=record)
class LDSTImmSaturationRM(LDSTImmBaseRM):
"""ld/st immediate: sat mode: N=0/1 u/s"""
els: BaseRM.mode[3]
RC1: BaseRM.mode[4]
+ def specifiers(self, record):
+ if self.RC1:
+ inv = "~" if self.inv else ""
+ yield f"pr={inv}RC1"
+
+ yield from super().specifiers(record=record)
class LDSTImmRM(LDSTImmBaseRM):
simple: LDSTImmSimpleRM
def specifiers(self, record):
if self.zz:
yield f"zz"
+ if self.RC1:
+ inv = "~" if self.inv else ""
+ yield f"pr={inv}RC1"
yield from super().specifiers(record=record)
def select(self, record, Rc):
rm = self
+ # the idea behind these tables is that they are now literally
+ # in identical format to insndb.csv and minor_xx.csv and can
+ # be done precisely as that. the only thing to watch out for
+ # is the insertion of Rc=1 as a "mask/value" bit and likewise
+ # regtype detection (3-bit BF/BFA, 5-bit BA/BB/BT) also inserted
+ # as the LSB.
table = None
if record.svp64.mode is _SVMode.NORMAL:
# concatenate mode 5-bit with Rc (LSB) then do a mask/map search
- # mode Rc mask Rc action(getattr)
+ # mode Rc mask Rc member
table = (
(0b000000, 0b111000, "simple"), # simple (no Rc)
(0b001000, 0b111000, "smr"), # mapreduce (no Rc)
elif record.svp64.mode is _SVMode.LDST_IMM:
# concatenate mode 5-bit with Rc (LSB) then do a mask/map search
- # mode Rc mask Rc action(getattr)
+ # mode Rc mask Rc member
# ironically/coincidentally this table is identical to NORMAL
# mode except reserved in place of smr
table = (
- (0b000000, 0b111000, "simple"), # simple (no Rc)
- (0b001000, 0b111000, "reserved"), # rsvd (no Rc)
- (0b010000, 0b110001, "ffrc0"), # ffirst, Rc=0
- (0b010001, 0b110001, "ffrc1"), # ffirst, Rc=1
- (0b100000, 0b110000, "sat"), # saturation (no Rc)
- (0b110000, 0b110001, "prrc0"), # predicate, Rc=0
- (0b110001, 0b110001, "prrc1"), # predicate, Rc=1
+ (0b000000, 0b111000, "simple"), # simple (no Rc)
+ (0b001000, 0b111000, "reserved"), # rsvd (no Rc)
+ (0b010000, 0b110001, "ffrc0"), # ffirst, Rc=0
+ (0b010001, 0b110001, "ffrc1"), # ffirst, Rc=1
+ (0b100000, 0b110000, "sat"), # saturation (no Rc)
+ (0b110000, 0b110001, "prrc0"), # predicate, Rc=0
+ (0b110001, 0b110001, "prrc1"), # predicate, Rc=1
)
rm = rm.ldst_imm
search = ((int(rm.mode) << 1) | Rc)
elif record.svp64.mode is _SVMode.LDST_IDX:
# concatenate mode 5-bit with Rc (LSB) then do a mask/map search
- # mode Rc mask Rc action(getattr)
+ # mode Rc mask Rc member
table = (
(0b000000, 0b111000, "simple"), # simple (no Rc)
(0b010000, 0b110000, "stride"), # strided, (no Rc)
search = ((int(rm.mode) << 1) | Rc)
elif record.svp64.mode is _SVMode.CROP:
- # concatenate mode 5-bit with Rc (LSB) then do a mask/map search
- # mode 3b mask 3b action(getattr)
+ # concatenate mode 5-bit with regtype (LSB) then do mask/map search
+ # mode 3b mask 3b member
table = (
(0b000000, 0b111000, "simple"), # simple
(0b001000, 0b111000, "smr"), # mapreduce
rm = rm.cr_op
search = ((int(rm.mode) << 1) | (regtype or 0))
+ elif record.svp64.mode is _SVMode.BRANCH:
+ # just mode 5-bit. could be reduced down to 2, oh well.
+ # mode mask action(getattr)
+ table = [(0b00000, 0b11000, "simple"), # simple
+ (0b01000, 0b11000, "vls"), # VLset
+ (0b10000, 0b11000, "ctr"), # CTR mode
+ (0b11000, 0b11000, "ctrvls"), # CTR+VLset mode
+ ]
+ # slightly weird: doesn't have a 5-bit "mode" field like others
+ search = int(rm[19:23])
+
# look up in table
if table is not None:
for (value, mask, member) in table:
rm = getattr(rm, member)
break
- elif record.svp64.mode is _SVMode.BRANCH:
- if rm[19] == 0b0:
- if rm[20] == 0b0:
- rm = rm.simple
- else:
- rm = rm.vls
- else:
- if rm[20] == 0b0:
- rm = rm.ctr
- else:
- rm = rm.ctrvls
-
if rm.__class__ is self.__class__:
raise ValueError(self)
Rc = False
if record.mdwn.operands["Rc"] is not None:
- Rc = bool(self.suffix[record.fields["Rc"]])
+ Rc = bool(record.mdwn.operands["Rc"].value)
rm = self.prefix.rm.select(record=record, Rc=Rc)
specifiers = tuple(rm.specifiers(record=record))