CryIn as _CryIn,
Form as _Form,
SVEtype as _SVEtype,
+ SVmask_src as _SVmask_src,
SVMode as _SVMode,
SVPtype as _SVPtype,
SVExtra as _SVExtra,
name: str
ptype: _SVPtype = _SVPtype.NONE
etype: _SVEtype = _SVEtype.NONE
+ msrc: _SVmask_src = _SVmask_src.NO # MASK_SRC is active
in1: _In1Sel = _In1Sel.NONE
in2: _In2Sel = _In2Sel.NONE
in3: _In3Sel = _In3Sel.NONE
"CONDITIONS": "conditions",
"Ptype": "ptype",
"Etype": "etype",
+ "SM": "msrc",
"CR in": "cr_in",
"CR out": "cr_out",
}
subvl: _Field = range(8, 10)
mode: Mode.remap(range(19, 24))
smask: _Field = range(16, 19)
-
extra: Extra.remap(range(10, 19))
extra2: Extra2.remap(range(10, 19))
extra3: Extra3.remap(range(10, 19))
+ def specifiers(self, record):
+ subvl = int(self.subvl)
+ if subvl > 0:
+ yield {
+ 1: "vec2",
+ 2: "vec3",
+ 3: "vec4",
+ }[subvl]
+
def disassemble(self, verbosity=Verbosity.NORMAL):
if verbosity >= Verbosity.VERBOSE:
indent = (" " * 4)
yield f"{indent}{', '.join(map(str, members))}"
-class NormalRM(BaseRM):
- class simple(BaseRM):
- """normal: simple mode"""
- dz: BaseRM.mode[3]
- sz: BaseRM.mode[4]
+class NormalLDSTBaseRM(BaseRM):
+ def specifiers(self, record):
+ widths = {
+ 0b11: "8",
+ 0b10: "16",
+ 0b01: "32",
+ }
+ predicates = {
+ # integer
+ (0, 0b001): "1<<r3",
+ (0, 0b010): "r3",
+ (0, 0b011): "~r3",
+ (0, 0b100): "r10",
+ (0, 0b101): "~r10",
+ (0, 0b110): "r30",
+ (0, 0b111): "~r30",
+ # CRs
+ (1, 0b000): "lt",
+ (1, 0b001): "ge",
+ (1, 0b010): "gt",
+ (1, 0b011): "le",
+ (1, 0b100): "eq",
+ (1, 0b101): "ne",
+ (1, 0b110): "so",
+ (1, 0b111): "ns",
+ }
- class smr(BaseRM):
- """normal: scalar reduce mode (mapreduce), SUBVL=1"""
- RG: BaseRM.mode[4]
+ mmode = int(self.mmode)
+ mask = int(self.mask)
+ if record.svp64.ptype is _SVPtype.P2:
+ (smask, dmask) = (int(self.smask), mask)
+ else:
+ (smask, dmask) = (mask, mask)
+ if all((smask, dmask)) and (smask == dmask):
+ yield f"m={predicates[(mmode, smask)]}"
+ else:
+ sw = predicates.get((mmode, smask))
+ dw = predicates.get((mmode, dmask))
+ if sw:
+ yield f"sm={sw}"
+ if dw:
+ yield f"dm={dw}"
+
+ dw = int(self.elwidth)
+ sw = int(self.ewsrc)
+ if all((dw, sw)) and (dw == sw):
+ yield f"w={widths[dw]}"
+ else:
+ if dw != 0b00:
+ yield f"dw={widths[dw]}"
+ if sw != 0b00:
+ yield f"sw={widths[sw]}"
+
+ yield from super().specifiers(record=record)
+
+
+class NormalBaseRM(NormalLDSTBaseRM):
+ pass
+
+
+class NormalSimpleRM(NormalBaseRM):
+ """normal: simple mode"""
+ dz: BaseRM.mode[3]
+ sz: BaseRM.mode[4]
+
+ def specifiers(self, record):
+ if self.dz:
+ yield f"dz"
+ if self.sz:
+ yield f"sz"
+ yield from super().specifiers(record=record)
+
+
+class NormalScalarReduceRM(NormalBaseRM):
+ """normal: scalar reduce mode (mapreduce), SUBVL=1"""
+ RG: BaseRM.mode[4]
+
+ def specifiers(self, record):
+ if self.RG:
+ yield "mrr"
+
+ yield from super().specifiers(record=record)
+
+
+class NormalReservedRM(NormalBaseRM):
+ """normal: reserved"""
+ pass
+
+
+class NormalFailFirstRc1RM(NormalBaseRM):
+ """normal: Rc=1: ffirst CR sel"""
+ inv: BaseRM.mode[2]
+ CR: BaseRM.mode[3, 4]
+
+
+class NormalFailFirstRc0RM(NormalBaseRM):
+ """normal: Rc=0: ffirst z/nonz"""
+ inv: BaseRM.mode[2]
+ VLi: BaseRM.mode[3]
+ RC1: BaseRM.mode[4]
+
+ def specifiers(self, record):
+ if self.RC1:
+ inv = "~" if self.inv else ""
+ yield f"ff={inv}RC1"
+
+ yield from super().specifiers(record=record)
+
+
+class NormalSaturationRM(NormalBaseRM):
+ """normal: sat mode: N=0/1 u/s, SUBVL=1"""
+ N: BaseRM.mode[2]
+ dz: BaseRM.mode[3]
+ sz: BaseRM.mode[4]
+
+ def specifiers(self, record):
+ if self.dz:
+ yield f"dz"
+ if self.sz:
+ yield f"sz"
+ if self.N:
+ yield "sats"
+ else:
+ yield "satu"
+
+ yield from super().specifiers(record=record)
+
+
+class NormalPredResultRc1RM(NormalBaseRM):
+ """normal: Rc=1: pred-result CR sel"""
+ inv: BaseRM.mode[2]
+ CR: BaseRM.mode[3, 4]
+
+
+class NormalPredResultRc0RM(NormalBaseRM):
+ """normal: Rc=0: pred-result z/nonz"""
+ inv: BaseRM.mode[2]
+ zz: BaseRM.mode[3]
+ RC1: BaseRM.mode[4]
+ dz: BaseRM.mode[3]
+ sz: BaseRM.mode[3]
+
+ def specifiers(self, record):
+ if self.zz:
+ yield f"zz"
+ if self.RC1:
+ inv = "~" if self.inv else ""
+ yield f"pr={inv}RC1"
+
+ yield from super().specifiers(record=record)
+
+
+class NormalRM(NormalBaseRM):
+ simple: NormalSimpleRM
+ smr: NormalScalarReduceRM
+ reserved: NormalReservedRM
+ ffrc1: NormalFailFirstRc1RM
+ ffrc0: NormalFailFirstRc0RM
+ sat: NormalSaturationRM
+ prrc1: NormalPredResultRc1RM
+ prrc0: NormalPredResultRc0RM
+
+
+class LDSTImmBaseRM(NormalLDSTBaseRM):
+ pass
+
+
+class LDSTImmSimpleRM(LDSTImmBaseRM):
+ """ld/st immediate: simple mode"""
+ zz: BaseRM.mode[3]
+ els: BaseRM.mode[4]
+ dz: BaseRM.mode[3]
+ sz: BaseRM.mode[3]
+
+ def specifiers(self, record):
+ if self.zz:
+ yield f"zz"
+
+ yield from super().specifiers(record=record)
+
+
+class LDSTImmReservedRM(LDSTImmBaseRM):
+ """ld/st immediate: reserved"""
+ pass
+
+
+class LDSTImmFailFirstRc1RM(LDSTImmBaseRM):
+ """ld/st immediate: Rc=1: ffirst CR sel"""
+ inv: BaseRM.mode[2]
+ CR: BaseRM.mode[3, 4]
+
+
+class LDSTImmFailFirstRc0RM(LDSTImmBaseRM):
+ """ld/st immediate: Rc=0: ffirst z/nonz"""
+ inv: BaseRM.mode[2]
+ els: BaseRM.mode[3]
+ RC1: BaseRM.mode[4]
+
+ def specifiers(self, record):
+ if self.RC1:
+ inv = "~" if self.inv else ""
+ yield f"ff={inv}RC1"
+
+ yield from super().specifiers(record=record)
+
+class LDSTImmSaturationRM(LDSTImmBaseRM):
+ """ld/st immediate: sat mode: N=0/1 u/s"""
+ N: BaseRM.mode[2]
+ zz: BaseRM.mode[3]
+ els: BaseRM.mode[4]
+ dz: BaseRM.mode[3]
+ sz: BaseRM.mode[3]
+
+ def specifiers(self, record):
+ if self.zz:
+ yield f"zz"
+ if self.N:
+ yield "sats"
+ else:
+ yield "satu"
+
+ yield from super().specifiers(record=record)
+
+
+class LDSTImmPredResultRc1RM(LDSTImmBaseRM):
+ """ld/st immediate: Rc=1: pred-result CR sel"""
+ inv: BaseRM.mode[2]
+ CR: BaseRM.mode[3, 4]
+
+
+class LDSTImmPredResultRc0RM(LDSTImmBaseRM):
+ """ld/st immediate: Rc=0: pred-result z/nonz"""
+ inv: BaseRM.mode[2]
+ els: BaseRM.mode[3]
+ RC1: BaseRM.mode[4]
+
+ def specifiers(self, record):
+ if self.RC1:
+ inv = "~" if self.inv else ""
+ yield f"pr={inv}RC1"
+
+ yield from super().specifiers(record=record)
+
+class LDSTImmRM(LDSTImmBaseRM):
+ simple: LDSTImmSimpleRM
+ reserved: LDSTImmReservedRM
+ ffrc1: LDSTImmFailFirstRc1RM
+ ffrc0: LDSTImmFailFirstRc0RM
+ sat: LDSTImmSaturationRM
+ prrc1: LDSTImmPredResultRc1RM
+ prrc0: LDSTImmPredResultRc0RM
+
+
+class LDSTIdxBaseRM(NormalLDSTBaseRM):
+ pass
- class pmr(BaseRM):
- """normal: parallel reduce mode (mapreduce), SUBVL=1"""
- pass
- class svmr(BaseRM):
- """normal: subvector reduce mode, SUBVL>1"""
- SVM: BaseRM.mode[3]
-
- class pu(BaseRM):
- """normal: Pack/Unpack mode, SUBVL>1"""
- SVM: BaseRM.mode[3]
-
- class ffrc1(BaseRM):
- """normal: Rc=1: ffirst CR sel"""
- inv: BaseRM.mode[2]
- CR: BaseRM.mode[3, 4]
-
- class ffrc0(BaseRM):
- """normal: Rc=0: ffirst z/nonz"""
- inv: BaseRM.mode[2]
- VLi: BaseRM.mode[3]
- RC1: BaseRM.mode[4]
-
- class sat(BaseRM):
- """normal: sat mode: N=0/1 u/s, SUBVL=1"""
- N: BaseRM.mode[2]
- dz: BaseRM.mode[3]
- sz: BaseRM.mode[4]
-
- class satx(BaseRM):
- """normal: sat mode: N=0/1 u/s, SUBVL>1"""
- N: BaseRM.mode[2]
- zz: BaseRM.mode[3]
- dz: BaseRM.mode[3]
- sz: BaseRM.mode[3]
-
- class satpu(BaseRM):
- """normal: Pack/Unpack sat mode: N=0/1 u/s, SUBVL>1"""
- N: BaseRM.mode[2]
- zz: BaseRM.mode[3]
- dz: BaseRM.mode[3]
- sz: BaseRM.mode[3]
-
- class prrc1(BaseRM):
- """normal: Rc=1: pred-result CR sel"""
- inv: BaseRM.mode[2]
- CR: BaseRM.mode[3, 4]
-
- class prrc0(BaseRM):
- """normal: Rc=0: pred-result z/nonz"""
- inv: BaseRM.mode[2]
- zz: BaseRM.mode[3]
- RC1: BaseRM.mode[4]
- dz: BaseRM.mode[3]
- sz: BaseRM.mode[3]
-
- simple: simple
- smr: smr
- pmr: pmr
- svmr: svmr
- pu: pu
- ffrc1: ffrc1
- ffrc0: ffrc0
- sat: sat
- satx: satx
- satpu: satpu
- prrc1: prrc1
- prrc0: prrc0
-
-
-class LDSTImmRM(BaseRM):
- class simple(BaseRM):
- """ld/st immediate: simple mode"""
- zz: BaseRM.mode[3]
- els: BaseRM.mode[4]
- dz: BaseRM.mode[3]
- sz: BaseRM.mode[3]
-
- class spu(BaseRM):
- """ld/st immediate: Structured Pack/Unpack"""
- zz: BaseRM.mode[3]
- els: BaseRM.mode[4]
- dz: BaseRM.mode[3]
- sz: BaseRM.mode[3]
-
- class ffrc1(BaseRM):
- """ld/st immediate: Rc=1: ffirst CR sel"""
- inv: BaseRM.mode[2]
- CR: BaseRM.mode[3, 4]
-
- class ffrc0(BaseRM):
- """ld/st immediate: Rc=0: ffirst z/nonz"""
- inv: BaseRM.mode[2]
- els: BaseRM.mode[3]
- RC1: BaseRM.mode[4]
-
- class sat(BaseRM):
- """ld/st immediate: sat mode: N=0/1 u/s"""
- N: BaseRM.mode[2]
- zz: BaseRM.mode[3]
- els: BaseRM.mode[4]
- dz: BaseRM.mode[3]
- sz: BaseRM.mode[3]
-
- class prrc1(BaseRM):
- """ld/st immediate: Rc=1: pred-result CR sel"""
- inv: BaseRM.mode[2]
- CR: BaseRM.mode[3, 4]
-
- class prrc0(BaseRM):
- """ld/st immediate: Rc=0: pred-result z/nonz"""
- inv: BaseRM.mode[2]
- els: BaseRM.mode[3]
- RC1: BaseRM.mode[4]
-
- simple: simple
- spu: spu
- ffrc1: ffrc1
- ffrc0: ffrc0
- sat: sat
- prrc1: prrc1
- prrc0: prrc0
-
-
-class LDSTIdxRM(BaseRM):
- class simple(BaseRM):
- """ld/st index: simple mode"""
- SEA: BaseRM.mode[2]
- sz: BaseRM.mode[3]
- dz: BaseRM.mode[3]
-
- class stride(BaseRM):
- """ld/st index: strided (scalar only source)"""
- SEA: BaseRM.mode[2]
- dz: BaseRM.mode[3]
- sz: BaseRM.mode[4]
-
- class sat(BaseRM):
- """ld/st index: sat mode: N=0/1 u/s"""
- N: BaseRM.mode[2]
- dz: BaseRM.mode[3]
- sz: BaseRM.mode[4]
-
- class prrc1(BaseRM):
- """ld/st index: Rc=1: pred-result CR sel"""
- inv: BaseRM.mode[2]
- CR: BaseRM.mode[3, 4]
-
- class prrc0(BaseRM):
- """ld/st index: Rc=0: pred-result z/nonz"""
- inv: BaseRM.mode[2]
- zz: BaseRM.mode[3]
- RC1: BaseRM.mode[4]
- dz: BaseRM.mode[3]
- sz: BaseRM.mode[3]
-
- simple: simple
- stride: stride
- sat: sat
- prrc1: prrc1
- prrc0: prrc0
-
-
-class CROpRM(BaseRM):
- class simple(BaseRM):
- """cr_op: simple mode"""
- sz: BaseRM[6]
- SNZ: BaseRM[7]
- RG: BaseRM[20]
- dz: BaseRM[22]
-
- class smr(BaseRM):
- """cr_op: scalar reduce mode (mapreduce), SUBVL=1"""
- sz: BaseRM[6]
- SNZ: BaseRM[7]
- RG: BaseRM[20]
-
- class svmr(BaseRM):
- """cr_op: subvector reduce mode, SUBVL>1"""
- zz: BaseRM[6]
- SNZ: BaseRM[7]
- RG: BaseRM[20]
- SVM: BaseRM[22]
- dz: BaseRM[6]
- sz: BaseRM[6]
-
- class reserved(BaseRM):
- """cr_op: reserved"""
- zz: BaseRM[6]
- SNZ: BaseRM[7]
- RG: BaseRM[20]
- dz: BaseRM[6]
- sz: BaseRM[6]
-
- class ff3(BaseRM):
- """cr_op: ffirst 3-bit mode"""
- zz: BaseRM[6]
- SNZ: BaseRM[7]
- VLI: BaseRM[20]
- inv: BaseRM[21]
- CR: BaseRM[22, 23]
- dz: BaseRM[6]
- sz: BaseRM[6]
-
- class ff5(BaseRM):
- """cr_op: ffirst 5-bit mode"""
- zz: BaseRM[6]
- SNZ: BaseRM[7]
- VLI: BaseRM[20]
- inv: BaseRM[21]
- dz: BaseRM[22]
- dz: BaseRM[6]
- sz: BaseRM[6]
-
- simple: simple
- smr: smr
- svmr: svmr
- reserved: reserved
- ff3: ff3
- ff5: ff5
+class LDSTIdxSimpleRM(LDSTIdxBaseRM):
+ """ld/st index: simple mode"""
+ SEA: BaseRM.mode[2]
+ sz: BaseRM.mode[3]
+ dz: BaseRM.mode[3]
+
+ def specifiers(self, record):
+ if self.dz:
+ yield f"dz"
+ if self.sz:
+ yield f"sz"
+
+ yield from super().specifiers(record=record)
+
+
+class LDSTIdxStrideRM(LDSTIdxBaseRM):
+ """ld/st index: strided (scalar only source)"""
+ SEA: BaseRM.mode[2]
+ dz: BaseRM.mode[3]
+ sz: BaseRM.mode[4]
+
+ def specifiers(self, record):
+ if self.dz:
+ yield f"dz"
+ if self.sz:
+ yield f"sz"
+
+ yield from super().specifiers(record=record)
+
+
+class LDSTIdxSaturationRM(LDSTIdxBaseRM):
+ """ld/st index: sat mode: N=0/1 u/s"""
+ N: BaseRM.mode[2]
+ dz: BaseRM.mode[3]
+ sz: BaseRM.mode[4]
+
+ def specifiers(self, record):
+ if self.dz:
+ yield f"dz"
+ if self.sz:
+ yield f"sz"
+ if self.N:
+ yield "sats"
+ else:
+ yield "satu"
+
+ yield from super().specifiers(record=record)
+
+
+class LDSTIdxPredResultRc1RM(LDSTIdxBaseRM):
+ """ld/st index: Rc=1: pred-result CR sel"""
+ inv: BaseRM.mode[2]
+ CR: BaseRM.mode[3, 4]
+
+
+class LDSTIdxPredResultRc0RM(LDSTIdxBaseRM):
+ """ld/st index: Rc=0: pred-result z/nonz"""
+ inv: BaseRM.mode[2]
+ zz: BaseRM.mode[3]
+ RC1: BaseRM.mode[4]
+ dz: BaseRM.mode[3]
+ sz: BaseRM.mode[3]
+
+ def specifiers(self, record):
+ if self.zz:
+ yield f"zz"
+ if self.RC1:
+ inv = "~" if self.inv else ""
+ yield f"pr={inv}RC1"
+
+ yield from super().specifiers(record=record)
+
+
+class LDSTIdxRM(LDSTIdxBaseRM):
+ simple: LDSTIdxSimpleRM
+ stride: LDSTIdxStrideRM
+ sat: LDSTIdxSaturationRM
+ prrc1: LDSTIdxPredResultRc1RM
+ prrc0: LDSTIdxPredResultRc0RM
+
+
+class CROpBaseRM(BaseRM):
+ pass
+
+
+class CROpSimpleRM(CROpBaseRM):
+ """cr_op: simple mode"""
+ sz: BaseRM[6]
+ SNZ: BaseRM[7]
+ RG: BaseRM[20]
+ dz: BaseRM[22]
+
+ def specifiers(self, record):
+ if self.dz:
+ yield f"dz"
+ if self.sz:
+ yield f"sz"
+ if self.RG:
+ yield "mrr"
+
+ yield from super().specifiers(record=record)
+
+
+class CROpScalarReduceRM(CROpBaseRM):
+ """cr_op: scalar reduce mode (mapreduce), SUBVL=1"""
+ sz: BaseRM[6]
+ SNZ: BaseRM[7]
+ RG: BaseRM[20]
+
+ def specifiers(self, record):
+ if self.sz:
+ yield f"sz"
+ if self.RG:
+ yield "mrr"
+
+ yield from super().specifiers(record=record)
+
+
+class CROpReservedRM(CROpBaseRM):
+ """cr_op: reserved"""
+ zz: BaseRM[6]
+ SNZ: BaseRM[7]
+ RG: BaseRM[20]
+ dz: BaseRM[6]
+ sz: BaseRM[6]
+
+ def specifiers(self, record):
+ if self.zz:
+ yield f"zz"
+ if self.RG:
+ yield "mrr"
+
+ yield from super().specifiers(record=record)
+
+
+class CROpFailFirst3RM(CROpBaseRM):
+ """cr_op: ffirst 3-bit mode"""
+ zz: BaseRM[6]
+ SNZ: BaseRM[7]
+ VLI: BaseRM[20]
+ inv: BaseRM[21]
+ CR: BaseRM[22, 23]
+ dz: BaseRM[6]
+ sz: BaseRM[6]
+
+ def specifiers(self, record):
+ if self.zz:
+ yield f"zz"
+ yield from super().specifiers(record=record)
+
+
+class CROpFailFirst5RM(CROpBaseRM):
+ """cr_op: ffirst 5-bit mode"""
+ sz: BaseRM[6]
+ SNZ: BaseRM[7]
+ VLI: BaseRM[20]
+ inv: BaseRM[21]
+ dz: BaseRM[22]
+
+ def specifiers(self, record):
+ if self.dz:
+ yield f"dz"
+ if self.sz:
+ yield f"sz"
+ yield from super().specifiers(record=record)
+
+
+class CROpRM(CROpBaseRM):
+ simple: CROpSimpleRM
+ smr: CROpScalarReduceRM
+ reserved: CROpReservedRM
+ ff3: CROpFailFirst3RM
+ ff5: CROpFailFirst5RM
class BranchBaseRM(BaseRM):
sz: BaseRM[23]
-class BranchRM(BranchBaseRM):
- class simple(BranchBaseRM):
- """branch: simple mode"""
- pass
+class BranchSimpleRM(BranchBaseRM):
+ """branch: simple mode"""
+ pass
- class vls(BranchBaseRM):
- """branch: VLSET mode"""
- VSb: BaseRM[7]
- VLI: BaseRM[21]
- class ctr(BranchBaseRM):
- """branch: CTR-test mode"""
- CTi: BaseRM[6]
+class BranchVLSRM(BranchBaseRM):
+ """branch: VLSET mode"""
+ VSb: BaseRM[7]
+ VLI: BaseRM[21]
- class ctrvls(vls, ctr):
- """branch: CTR-test+VLSET mode"""
- pass
+
+class BranchCTRRM(BranchBaseRM):
+ """branch: CTR-test mode"""
+ CTi: BaseRM[6]
+
+
+class BranchCTRVLSRM(BranchVLSRM, BranchCTRRM):
+ """branch: CTR-test+VLSET mode"""
+ pass
+
+
+class BranchRM(BranchBaseRM):
+ simple: BranchSimpleRM
+ vls: BranchVLSRM
+ ctr: BranchCTRRM
+ ctrvls: BranchCTRVLSRM
class RM(BaseRM):
def select(self, record, Rc):
rm = self
+ # the idea behind these tables is that they are now literally
+ # in identical format to insndb.csv and minor_xx.csv and can
+ # be done precisely as that. the only thing to watch out for
+ # is the insertion of Rc=1 as a "mask/value" bit and likewise
+ # regtype detection (3-bit BF/BFA, 5-bit BA/BB/BT) also inserted
+ # as the LSB.
+ table = None
if record.svp64.mode is _SVMode.NORMAL:
+ # concatenate mode 5-bit with Rc (LSB) then do a mask/map search
+ # mode Rc mask Rc member
+ table = (
+ (0b000000, 0b111000, "simple"), # simple (no Rc)
+ (0b001000, 0b111000, "smr"), # mapreduce (no Rc)
+ (0b010000, 0b110001, "ffrc0"), # ffirst, Rc=0
+ (0b010001, 0b110001, "ffrc1"), # ffirst, Rc=1
+ (0b100000, 0b110000, "sat"), # saturation (no Rc)
+ (0b110000, 0b110001, "prrc0"), # predicate, Rc=0
+ (0b110001, 0b110001, "prrc1"), # predicate, Rc=1
+ )
rm = rm.normal
- if rm.mode[0:2] == 0b00:
- if rm.mode[2] == 0b0:
- rm = rm.simple
- else:
- if self.subvl == 0b00:
- if rm.mode[3] == 0b0:
- rm = rm.smr
- else:
- rm = rm.pmr
- else:
- if rm.mode[4] == 0b0:
- rm = rm.svmr
- else:
- rm = rm.pu
- elif rm.mode[0:2] == 0b01:
- if Rc:
- rm = rm.ffrc1
- else:
- rm = rm.ffrc0
- elif rm.mode[0:2] == 0b10:
- if self.subvl == 0b00:
- rm = rm.sat
- else:
- if rm.mode[4]:
- rm = rm.satx
- else:
- rm = rm.satpu
- elif rm.mode[0:2] == 0b11:
- if Rc:
- rm = rm.prrc1
- else:
- rm = rm.prrc0
+ search = ((int(rm.mode) << 1) | Rc)
elif record.svp64.mode is _SVMode.LDST_IMM:
+ # concatenate mode 5-bit with Rc (LSB) then do a mask/map search
+ # mode Rc mask Rc member
+ # ironically/coincidentally this table is identical to NORMAL
+ # mode except reserved in place of smr
+ table = (
+ (0b000000, 0b111000, "simple"), # simple (no Rc)
+ (0b001000, 0b111000, "reserved"), # rsvd (no Rc)
+ (0b010000, 0b110001, "ffrc0"), # ffirst, Rc=0
+ (0b010001, 0b110001, "ffrc1"), # ffirst, Rc=1
+ (0b100000, 0b110000, "sat"), # saturation (no Rc)
+ (0b110000, 0b110001, "prrc0"), # predicate, Rc=0
+ (0b110001, 0b110001, "prrc1"), # predicate, Rc=1
+ )
rm = rm.ldst_imm
- if rm.mode[0:2] == 0b00:
- if rm.mode[2] == 0b0:
- rm = rm.simple
- else:
- rm = rm.spu
- elif rm.mode[0:2] == 0b01:
- if Rc:
- rm = rm.ffrc1
- else:
- rm = rm.ffrc0
- elif rm.mode[0:2] == 0b10:
- rm = rm.sat
- elif rm.mode[0:2] == 0b11:
- if Rc:
- rm = rm.prrc1
- else:
- rm = rm.prrc0
-
- elif record.svp64.mode is _SVMode.LDST_IMM:
+ search = ((int(rm.mode) << 1) | Rc)
+
+ elif record.svp64.mode is _SVMode.LDST_IDX:
+ # concatenate mode 5-bit with Rc (LSB) then do a mask/map search
+ # mode Rc mask Rc member
+ table = (
+ (0b000000, 0b111000, "simple"), # simple (no Rc)
+ (0b010000, 0b110000, "stride"), # strided, (no Rc)
+ (0b100000, 0b110000, "sat"), # saturation (no Rc)
+ (0b110000, 0b110001, "prrc0"), # predicate, Rc=0
+ (0b110001, 0b110001, "prrc1"), # predicate, Rc=1
+ )
rm = rm.ldst_idx
- if rm.mode[0:2] == 0b00:
- rm = rm.simple
- elif rm.mode[0:2] == 0b01:
- rm = rm.stride
- elif rm.mode[0:2] == 0b10:
- rm = rm.sat
- elif rm.mode[0:2] == 0b11:
- if Rc:
- rm = rm.prrc1
- else:
- rm = rm.prrc0
+ search = ((int(rm.mode) << 1) | Rc)
elif record.svp64.mode is _SVMode.CROP:
- rm = rm.cr_op
- if rm[19] == 0b0:
- if rm[21] == 0b0:
- rm = rm.simple
- else:
- if self.subvl == 0:
- rm = rm.smr
- else:
- if rm[23] == 0b0:
- rm = rm.svmr
- else:
- rm = rm.reserved
+ # concatenate mode 5-bit with regtype (LSB) then do mask/map search
+ # mode 3b mask 3b member
+ table = (
+ (0b000000, 0b111000, "simple"), # simple
+ (0b001000, 0b111000, "smr"), # mapreduce
+ (0b100000, 0b100000, "ff5"), # failfirst, 5-bit CR
+ (0b100001, 0b100001, "ff3"), # failfirst, 3-bit CR
+ )
+ # determine CR type, 5-bit (BA/BB/BT) or 3-bit Field (BF/BFA)
+ regtype = None
+ for idx in range(0, 4):
+ for entry in record.svp64.extra[idx]:
+ if entry.regtype is _SVExtraRegType.DST:
+ if regtype is not None:
+ raise ValueError(record.svp64)
+ regtype = _RegType(entry.reg)
+ if regtype is _RegType.CR_REG:
+ regtype = 0 # 5-bit
+ elif regtype is _RegType.CR_BIT:
+ regtype = 1 # 3-bit
else:
- regtype = None
- for idx in range(0, 4):
- for entry in record.svp64.extra[idx]:
- if entry.regtype is _SVExtraRegType.DST:
- if regtype is not None:
- raise ValueError(record.svp64)
- regtype = _RegType(entry.reg)
- if regtype is _RegType.CR_REG:
- rm = rm.ff5
- elif regtype is _RegType.CR_BIT:
- rm = rm.ff3
- else:
- raise ValueError(record.svp64)
+ raise ValueError(record.svp64)
+ # finally provide info for search
+ rm = rm.cr_op
+ search = ((int(rm.mode) << 1) | (regtype or 0))
elif record.svp64.mode is _SVMode.BRANCH:
- if rm[19] == 0b0:
- if rm[20] == 0b0:
- rm = rm.simple
- else:
- rm = rm.vls
- else:
- if rm[20] == 0b0:
- rm = rm.ctr
- else:
- rm = rm.ctrvls
+ # just mode 5-bit. could be reduced down to 2, oh well.
+ # mode mask action(getattr)
+ table = [(0b00000, 0b11000, "simple"), # simple
+ (0b01000, 0b11000, "vls"), # VLset
+ (0b10000, 0b11000, "ctr"), # CTR mode
+ (0b11000, 0b11000, "ctrvls"), # CTR+VLset mode
+ ]
+ # slightly weird: doesn't have a 5-bit "mode" field like others
+ search = int(rm[19:23])
+
+ # look up in table
+ if table is not None:
+ for (value, mask, member) in table:
+ if ((value & search) == (mask & search)):
+ rm = getattr(rm, member)
+ break
if rm.__class__ is self.__class__:
raise ValueError(self)
yield f"{blob_suffix}.long 0x{int(self.suffix):08x}"
return
+ name = f"sv.{record.name}"
+
+ Rc = False
+ if record.mdwn.operands["Rc"] is not None:
+ Rc = bool(record.mdwn.operands["Rc"].value)
+ rm = self.prefix.rm.select(record=record, Rc=Rc)
+
+ specifiers = tuple(rm.specifiers(record=record))
+ if specifiers:
+ specifiers = "/".join(specifiers)
+ specifiers = f"/{specifiers}"
+ else:
+ specifiers = ""
+
operands = tuple(map(_operator.itemgetter(1),
self.dynamic_operands(db=db, verbosity=verbosity)))
if operands:
- yield f"{blob_prefix}sv.{record.name} {','.join(operands)}"
+ operands = f" {','.join(operands)}"
else:
- yield f"{blob_prefix}{record.name}"
+ operands = ""
+
+ yield f"{blob_prefix}{name}{specifiers}{operands}"
if blob_suffix:
yield f"{blob_suffix}"
- Rc = False
- if record.mdwn.operands["Rc"] is not None:
- Rc = bool(self.suffix[record.fields["Rc"]])
-
- rm = self.prefix.rm.select(record=record, Rc=Rc)
if verbosity >= Verbosity.VERBOSE:
indent = (" " * 4)
binary = self.binary