# Funded by NLnet http://nlnet.nl
from openpower.decoder.power_enums import get_csv, find_wiki_dir
+from openpower.util import log
import os
# identifies register by type
def is_GPR(regname):
return regname in ['RA', 'RB', 'RC', 'RS', 'RT']
+def is_FPR(regname):
+ return regname in ['FRA', 'FRB', 'FRC', 'FRS', 'FRT']
+
def get_regtype(regname):
if is_CR_3bit(regname):
return "CR_3bit"
return "CR_5bit"
if is_GPR(regname):
return "GPR"
+ if is_FPR(regname):
+ return "FPR"
def decode_extra(rm, prefix=''):
dest_reg_cr, src_reg_cr = False, False
svp64_srcreg_byname = {}
svp64_destreg_byname = {}
+ log ("decode_extra RM", rm)
for i in range(4):
- print (rm)
rfield = rm[prefix+str(i)]
if not rfield or rfield == '0':
continue
- print ("EXTRA field", i, rfield)
+ log ("EXTRA field", i, rfield)
rfield = rfield.split(";") # s:RA;d:CR1 etc.
for r in rfield:
rtype = r[0]
for fname in os.listdir(pth):
if fname.startswith("RM") or fname.startswith("LDSTRM"):
for entry in get_csv(fname):
+ entry['insn'] = entry['insn'].split("=")[-1]
if microwatt_format:
# move RS from position 1 to position 3, to match
# microwatt decode1.vhdl format
# now add the RM fields (for each instruction)
for entry in v30b:
+ # FP entries have a format NN/NN=insn
+ entry['comment'] = entry['comment'].split("=")[-1]
# *sigh* create extra field "out2" based on LD/ST update
# KEEP TRACK HERE https://bugs.libre-soc.org/show_bug.cgi?id=619
entry['out2'] = 'NONE'
# dummy (blank) fields, first
entry.update({'EXTRA0': '0', 'EXTRA1': '0', 'EXTRA2': '0',
'EXTRA3': '0',
+ 'SV_mode': 'NONE',
'SV_Ptype': 'NONE', 'SV_Etype': 'NONE',
'sv_cr_in': 'NONE', 'sv_cr_out': 'NONE'})
for fname in ['in1', 'in2', 'in3', 'out', 'out2']:
svp64 = self.instrs[asmcode]
for k, v in {'EXTRA0': '0', 'EXTRA1': '1', 'EXTRA2': '2',
'EXTRA3': '3',
+ 'SV_mode': 'mode',
'SV_Ptype': 'Ptype', 'SV_Etype': 'Etype'}.items():
entry[k] = svp64[v]
extra_index = None
if regfield == 'RA_OR_ZERO':
regfield = 'RA'
- print (asmcode, regfield, fname, svp64_dest, svp64_src)
+ log (asmcode, regfield, fname, svp64_dest, svp64_src)
# find the reg in the SVP64 extra map
if (fname in ['out', 'out2'] and regfield in svp64_dest):
extra_index = svp64_dest[regfield]
print (entry)
minor_31 = isa.get_svp64_csv("minor_31.csv")
for entry in minor_31:
- print (entry)
+ if entry['comment'].startswith('cmp'):
+ print ("cmp", entry)