# Funded by NLnet http://nlnet.nl
from openpower.decoder.power_enums import get_csv, find_wiki_dir
+from openpower.util import log
import os
# identifies register by type
return "FPR"
-def decode_extra(rm, prefix='', verbose=False):
+def decode_extra(rm, prefix=''):
# first turn the svp64 rm into a "by name" dict, recording
# which position in the RM EXTRA it goes into
# also: record if the src or dest was a CR, for sanity-checking
dest_reg_cr, src_reg_cr = False, False
svp64_srcreg_byname = {}
svp64_destreg_byname = {}
+ log ("decode_extra RM", rm)
for i in range(4):
- if verbose:
- print (rm)
rfield = rm[prefix+str(i)]
if not rfield or rfield == '0':
continue
- if verbose:
- print ("EXTRA field", i, rfield)
+ log ("EXTRA field", i, rfield)
rfield = rfield.split(";") # s:RA;d:CR1 etc.
for r in rfield:
rtype = r[0]
"""
self.instrs = {}
self.svp64_instrs = {}
- self.verbose = False
pth = find_wiki_dir()
for fname in os.listdir(pth):
if fname.startswith("RM") or fname.startswith("LDSTRM"):
# hmm, we need something more useful: a cross-association
# of the in1/2/3 and CR in/out with the EXTRA0-3 fields
- decode = decode_extra(entry, "EXTRA", self.verbose)
+ decode = decode_extra(entry, "EXTRA")
dest_reg_cr, src_reg_cr, svp64_src, svp64_dest = decode
# now examine in1/2/3/out, create sv_in1/2/3/out
extra_index = None
if regfield == 'RA_OR_ZERO':
regfield = 'RA'
- if self.verbose:
- print (asmcode, regfield, fname, svp64_dest, svp64_src)
+ log (asmcode, regfield, fname, svp64_dest, svp64_src)
# find the reg in the SVP64 extra map
if (fname in ['out', 'out2'] and regfield in svp64_dest):
extra_index = svp64_dest[regfield]