# Funded by NLnet http://nlnet.nl
from openpower.decoder.power_enums import get_csv, find_wiki_dir
+from openpower.util import log
import os
# identifies register by type
def is_GPR(regname):
return regname in ['RA', 'RB', 'RC', 'RS', 'RT']
+def is_FPR(regname):
+ return regname in ['FRA', 'FRB', 'FRC', 'FRS', 'FRT']
+
def get_regtype(regname):
if is_CR_3bit(regname):
return "CR_3bit"
return "CR_5bit"
if is_GPR(regname):
return "GPR"
+ if is_FPR(regname):
+ return "FPR"
def decode_extra(rm, prefix=''):
dest_reg_cr, src_reg_cr = False, False
svp64_srcreg_byname = {}
svp64_destreg_byname = {}
+ log ("decode_extra RM", rm)
for i in range(4):
- print (rm)
rfield = rm[prefix+str(i)]
if not rfield or rfield == '0':
continue
- print ("EXTRA field", i, rfield)
+ log ("EXTRA field", i, rfield)
rfield = rfield.split(";") # s:RA;d:CR1 etc.
for r in rfield:
rtype = r[0]
extra_index = None
if regfield == 'RA_OR_ZERO':
regfield = 'RA'
- print (asmcode, regfield, fname, svp64_dest, svp64_src)
+ log (asmcode, regfield, fname, svp64_dest, svp64_src)
# find the reg in the SVP64 extra map
if (fname in ['out', 'out2'] and regfield in svp64_dest):
extra_index = svp64_dest[regfield]