power_insn: refactor opcode matching

[openpower-isa.git] / src / openpower / decoder / power_svp64_rm.py

diff --git a/src/openpower/decoder/power_svp64_rm.py b/src/openpower/decoder/power_svp64_rm.py
index 702bd8274f833367dbbb3561ed8fdcd45e9c80be..85492ddbf215f2fc34ed56b84bbfe504bc4d739b 100644 (file)
--- a/src/openpower/decoder/power_svp64_rm.py
+++ b/src/openpower/decoder/power_svp64_rm.py
@@ -66,16 +66,19 @@ LD/ST indexed:
 11     inv     zz RC1  Rc=0: pred-result z/nonz
 
 Arithmetic:
-00     0   dz sz       normal mode
-00     1   0 RG        scalar reduce mode (mapreduce), SUBVL=1
-00     1   1 /         parallel reduce mode (mapreduce), SUBVL=1
-00     1   SVM 0       subvector reduce mode, SUBVL>1
-00     1   SVM 1       Pack/Unpack mode, SUBVL>1
-01     inv CR-bit      Rc=1: ffirst CR sel
-01     inv VLi RC1     Rc=0: ffirst z/nonz
-10     N   dz sz       sat mode: N=0/1 u/s
-11     inv CR-bit      Rc=1: pred-result CR sel
-11     inv zz RC1      Rc=0: pred-result z/nonz 
+| 0-1 |  2  |  3   4  |  description              |
+| --- | --- |---------|-------------------------- |
+| 00  |   0 |  dz  sz | simple mode                      |
+| 00  |   1 | 0  RG   | scalar reduce mode (mapreduce), SUBVL=1 |
+| 00  |   1 | SVM 0   | subvector reduce mode, SUBVL>1   |
+| 00  |   1 | SVM 1   | Pack/Unpack mode, SUBVL>1   |
+| 01  | inv | CR-bit  | Rc=1: ffirst CR sel              |
+| 01  | inv | VLi RC1 |  Rc=0: ffirst z/nonz |
+| 10  |   N | dz   sz |  sat mode: N=0/1 u/s, SUBVL=1 |
+| 10  |   N | zz   0  |  sat mode: N=0/1 u/s, SUBVL>1 |
+| 10  |   N | zz   1  |  Pack/Unpack sat mode: N=0/1 u/s, SUBVL>1 |
+| 11  | inv | CR-bit  |  Rc=1: pred-result CR sel |
+| 11  | inv | zz  RC1 |  Rc=0: pred-result z/nonz |
 
 Branch Conditional:
 note that additional BC modes are in *other bits*, specifically
@@ -193,7 +196,7 @@ class SVP64RMModeDecode(Elaboratable):
             with m.If((~is_ldst) &                     # not for LD/ST
                         (mode2 == 0) &                 # first 2 bits == 0
                         mode[SVP64MODE.REDUCE] &       # bit 2 == 1
-                       (~mode[SVP64MODE.PARALLEL])):   # not parallel mapreduce
+                       (~mode[SVP64MODE.MOD3])):       # bit 3 == 0
                 comb += self.reverse_gear.eq(mode[SVP64MODE.RG]) # finally whew
 
             # extract zeroing