from nmigen.back.pysim import Simulator, Delay, Settle
from nmutil.formaltest import FHDLTestCase
import unittest
-from soc.decoder.power_decoder import (create_pdecode)
-from soc.decoder.power_enums import (Function, MicrOp,
+from openpower.decoder.power_decoder import (create_pdecode)
+from openpower.decoder.power_enums import (Function, MicrOp,
In1Sel, In2Sel, In3Sel,
OutSel, RC, LdstLen, CryIn,
single_bit_flags, Form, SPR,
get_signal_name, get_csv)
-from soc.decoder.power_decoder2 import (PowerDecode2)
-from soc.simulator.program import Program
-from soc.simulator.qemu import run_program
-from soc.decoder.isa.all import ISA
-from soc.fu.test.common import TestCase
-from soc.simulator.test_sim import DecoderBase
-from soc.config.endian import bigendian
+from openpower.decoder.power_decoder2 import (PowerDecode2)
+from openpower.simulator.program import Program
+from openpower.simulator.qemu import run_program
+from openpower.decoder.isa.all import ISA
+from openpower.test.common import TestCase
+from openpower.simulator.test_sim import DecoderBase
+from openpower.endian import bigendian