speed up bytes upload in qemu.py

[openpower-isa.git] / src / openpower / simulator / test_sim.py

diff --git a/src/openpower/simulator/test_sim.py b/src/openpower/simulator/test_sim.py
index 4d586fa7808fd7fb8f23ce9551742feed3eb8213..03d7d8290a8da80e8346d386d790276d5062e066 100644 (file)
--- a/src/openpower/simulator/test_sim.py
+++ b/src/openpower/simulator/test_sim.py
@@ -1,19 +1,14 @@
-from nmigen import Module, Signal
+import unittest
+from nmigen import Module
 from nmigen.back.pysim import Simulator, Delay, Settle
 from nmutil.formaltest import FHDLTestCase
-import unittest
-from soc.decoder.power_decoder import (create_pdecode)
-from soc.decoder.power_enums import (Function, MicrOp,
-                                     In1Sel, In2Sel, In3Sel,
-                                     OutSel, RC, LdstLen, CryIn,
-                                     single_bit_flags, Form,
-                                     get_signal_name, get_csv)
-from soc.decoder.power_decoder2 import (PowerDecode2)
-from soc.simulator.program import Program
-from soc.simulator.qemu import run_program
-from soc.decoder.isa.all import ISA
-from soc.fu.test.common import TestCase
-from soc.config.endian import bigendian
+from openpower.decoder.power_decoder import create_pdecode
+from openpower.decoder.power_decoder2 import (PowerDecode2)
+from openpower.simulator.program import Program
+from openpower.simulator.qemu import run_program
+from openpower.decoder.isa.all import ISA
+from openpower.test.common import TestCase
+from openpower.endian import bigendian
 
 
 class AttnTestCase(FHDLTestCase):
@@ -554,7 +549,7 @@ class DecoderBase:
         print("sim xer", hex(sim_xer))
         self.assertEqual(qpc, sim_pc)
         for reg in regs:
-            qemu_val = qemu.get_register(reg)
+            qemu_val = qemu.get_gpr(reg)
             sim_val = sim.gpr(reg).value
             self.assertEqual(qemu_val, sim_val,
                              "expect %x got %x" % (qemu_val, sim_val))