use the CSV "CR out" column to compute which mode to use for Rc=1

[openpower-isa.git] / src / openpower / simulator / test_sim.py

diff --git a/src/openpower/simulator/test_sim.py b/src/openpower/simulator/test_sim.py
index 4d586fa7808fd7fb8f23ce9551742feed3eb8213..7c240bd8943c46b0a6e072817140d8443105508f 100644 (file)
--- a/src/openpower/simulator/test_sim.py
+++ b/src/openpower/simulator/test_sim.py
@@ -1,19 +1,14 @@
-from nmigen import Module, Signal
-from nmigen.back.pysim import Simulator, Delay, Settle
-from nmutil.formaltest import FHDLTestCase
 import unittest
-from soc.decoder.power_decoder import (create_pdecode)
-from soc.decoder.power_enums import (Function, MicrOp,
-                                     In1Sel, In2Sel, In3Sel,
-                                     OutSel, RC, LdstLen, CryIn,
-                                     single_bit_flags, Form,
-                                     get_signal_name, get_csv)
-from soc.decoder.power_decoder2 import (PowerDecode2)
-from soc.simulator.program import Program
-from soc.simulator.qemu import run_program
-from soc.decoder.isa.all import ISA
-from soc.fu.test.common import TestCase
-from soc.config.endian import bigendian
+from nmigen import Module
+from nmigen.sim import Simulator, Delay, Settle
+from nmutil.formaltest import FHDLTestCase
+from openpower.decoder.power_decoder import create_pdecode
+from openpower.decoder.power_decoder2 import (PowerDecode2)
+from openpower.simulator.program import Program
+from openpower.simulator.qemu import run_program
+from openpower.decoder.isa.all import ISA
+from openpower.test.common import TestCase
+from openpower.endian import bigendian
 
 
 class AttnTestCase(FHDLTestCase):
@@ -458,6 +453,14 @@ class GeneralTestCases(FHDLTestCase):
         with Program(lst, bigendian) as program:
             self.run_tst_program(program, [0, 1, 2])
 
+    def test_stfd(self):
+        """test FP store
+        """
+        lst = ["stfd f29, 0(1)",
+               ]
+        with Program(lst, bigendian) as program:
+            self.run_tst_program(program, [9], initial_mem={})
+
     def run_tst_program(self, prog, initial_regs=None, initial_sprs=None,
                         initial_mem=None):
         initial_regs = [0] * 32
@@ -554,7 +557,7 @@ class DecoderBase:
         print("sim xer", hex(sim_xer))
         self.assertEqual(qpc, sim_pc)
         for reg in regs:
-            qemu_val = qemu.get_register(reg)
+            qemu_val = qemu.get_gpr(reg)
             sim_val = sim.gpr(reg).value
             self.assertEqual(qemu_val, sim_val,
                              "expect %x got %x" % (qemu_val, sim_val))