got sv.bc working for pospopcount

[openpower-isa.git] / src / openpower / simulator / test_trap_sim.py

diff --git a/src/openpower/simulator/test_trap_sim.py b/src/openpower/simulator/test_trap_sim.py
index 1c79482639aa88c4511984ac217406693dc62b8e..e8f08b3b44cbd3a19ea54220572e325b10119697 100644 (file)
--- a/src/openpower/simulator/test_trap_sim.py
+++ b/src/openpower/simulator/test_trap_sim.py
@@ -1,20 +1,10 @@
-from nmigen import Module, Signal
-from nmigen.back.pysim import Simulator, Delay, Settle
 from nmutil.formaltest import FHDLTestCase
 import unittest
-from soc.decoder.power_decoder import (create_pdecode)
-from soc.decoder.power_enums import (Function, MicrOp,
-                                     In1Sel, In2Sel, In3Sel,
-                                     OutSel, RC, LdstLen, CryIn,
-                                     single_bit_flags, Form, SPR,
-                                     get_signal_name, get_csv)
-from soc.decoder.power_decoder2 import (PowerDecode2)
-from soc.simulator.program import Program
-from soc.simulator.qemu import run_program
-from soc.decoder.isa.all import ISA
-from soc.fu.test.common import TestCase
-from soc.simulator.test_sim import DecoderBase
-from soc.config.endian import bigendian
+from openpower.simulator.program import Program
+from openpower.simulator.qemu import run_program
+from openpower.test.common import TestCase
+from openpower.simulator.test_sim import DecoderBase
+from openpower.endian import bigendian #XXX HACK!
 
 
 class TrapSimTestCases(FHDLTestCase):