if insn_name == 'mtspr':
res['0'] = 'd:SPR' # SPR: Rdest1_EXTRA3
res['1'] = 's:RS' # RS: Rsrc1_EXTRA3
+ elif insn_name == 'rlwinm':
+ # weird one, RA is a dest but not in bits 6:10
+ res['0'] = 'd:RA;d:CR0' # RA: Rdest1_EXTRA3
+ res['1'] = 's:RS' # RS: Rsrc1_EXTRA3
elif insn_name == 'mfspr':
res['0'] = 'd:RS' # RS: Rdest1_EXTRA3
res['1'] = 's:SPR' # SPR: Rsrc1_EXTRA3
elif 'mfcr' in insn_name or 'mfocrf' in insn_name:
res['0'] = 'd:RT' # RT: Rdest1_EXTRA3
res['1'] = 's:CR' # CR: Rsrc1_EXTRA3
+ elif regs == ['', '', '', 'RT', 'BI', '']:
+ res['0'] = 'd:RT' # RT: Rdest1_EXTRA3
+ res['1'] = 's:BI' # BI: Rsrc1_EXTRA3
elif insn_name == 'setb':
res['0'] = 'd:RT' # RT: Rdest1_EXTRA3
res['1'] = 's:BFA' # BFA: Rsrc1_EXTRA3
elif regs == ['', 'FRB', '', 'FRT', '', 'CR1']:
res['0'] = 'd:FRT;d:CR1' # FRT,CR1: Rdest1_EXTRA3
res['1'] = 's:FRB' # FRB: Rsrc1_EXTRA3
+ elif regs == ['', 'RB', '', 'FRT', '', 'CR1']:
+ res['0'] = 'd:FRT;d:CR1' # FRT,CR1: Rdest1_EXTRA3
+ res['1'] = 's:RB' # RB: Rsrc1_EXTRA3
+ elif regs == ['', 'RB', '', 'FRT', '', '']:
+ res['0'] = 'd:FRT' # FRT: Rdest1_EXTRA3
+ res['1'] = 's:RB' # RB: Rsrc1_EXTRA3
+ elif regs == ['', 'FRB', '', 'RT', '', 'CR0']:
+ res['0'] = 'd:RT;d:CR0' # RT,CR0: Rdest1_EXTRA3
+ res['1'] = 's:FRB' # FRB: Rsrc1_EXTRA3
elif insn_name == 'fishmv':
# an overwrite instruction
res['0'] = 'd:FRS' # FRS: Rdest1_EXTRA3
res['0'] = 'd:RT' # RT: Rdest1_EXTRA3
res['1'] = 's:RA' # RS: Rsrc1_EXTRA3
else:
- res['0'] = 'TODO'
- print("regs TODO", insn_name, regs)
+ raise NotImplementedError(insn_name)
elif value == 'RM-1P-2S1D':
res['Etype'] = 'EXTRA3' # RM EXTRA3 type
res['0'] = 'd:FRT;d:CR1' # FRT,CR1: Rdest1_EXTRA3
res['1'] = 's:FRA' # FRA: Rsrc1_EXTRA3
res['2'] = 's:RB' # RB: Rsrc1_EXTRA3
+ elif regs == ['RS', 'RB', '', 'RA', '', '']:
+ res['0'] = 'd:RA' # RA: Rdest1_EXTRA3
+ res['1'] = 's:RS' # RS: Rsrc1_EXTRA3
+ res['2'] = 's:RB' # RB: Rsrc1_EXTRA3
elif name == '2R-1W' or insn_name == 'cmpb': # cmpb
if insn_name in ['bpermd', 'cmpb']:
res['0'] = 'd:RA' # RA: Rdest1_EXTRA3
res['0'] = 'd:RA;d:CR0' # RA,CR0: Rdest1_EXTRA3
res['1'] = 's:RA' # RA: Rsrc1_EXTRA3
res['2'] = 's:RS' # RS: Rsrc1_EXTRA3
+ elif regs == ['RA', '', 'RB', 'RT', '', '']: # maddsubrs
+ res['0'] = 's:RT;d:RT' # RT: Rdest1_EXTRA2
+ res['1'] = 's:RA' # RA: Rsrc1_EXTRA2
+ res['2'] = 's:RB' # RT: Rsrc2_EXTRA2
else:
- res['0'] = 'TODO'
+ raise NotImplementedError(insn_name)
elif value == 'RM-2P-2S1D':
res['Etype'] = 'EXTRA2' # RM EXTRA2 type
res['1'] = 's:RS' # RS: Rsrc1_EXTRA2
res['2'] = 's:CR' # CR: Rsrc2_EXTRA2
else:
- res['0'] = 'TODO'
+ raise NotImplementedError(insn_name)
elif value == 'RM-1P-3S1D':
res['Etype'] = 'EXTRA2' # RM EXTRA2 type
res['0'] = 's:RT;d:RT;d:CR0' # RT,CR0: Rdest1_EXTRA2
res['1'] = 's:RA' # RA: Rsrc1_EXTRA2
res['2'] = 's:RB' # RT: Rsrc2_EXTRA2
- elif regs == ['RA', 'RB', 'RT', 'RT', '', '']: # maddsubrs
- res['0'] = 's:RT;d:RT' # RT: Rdest1_EXTRA2
- res['1'] = 's:RA' # RA: Rsrc1_EXTRA2
- res['2'] = 's:RB' # RT: Rsrc2_EXTRA2
elif insn_name == 'isel':
res['0'] = 'd:RT' # RT: Rdest1_EXTRA2
res['1'] = 's:RA' # RA: Rsrc1_EXTRA2
if insn_name.startswith('bc'):
res['0'] = 's:BI' # BI: Rsrc1_EXTRA3
+ elif value == 'RM-1P-1S':
+ pass # FIXME
+
+ elif value == 'non-SV':
+ return
+
+ else:
+ raise NotImplementedError(insn_name)
+
+ #if insn_name.startswith("rlw"):
+ # print("regs ", value, insn_name, regs, res)
+
+
def process_csvs(format):
'2R-1W-CRo': 'RM-1P-2S1D',
'2R': 'non-SV',
'2R-1W': 'RM-1P-2S1D',
+ '2R-1W-imm': 'RM-1P-2S1D',
'1R-CRio': 'RM-2P-2S1D',
'2R-CRio': 'RM-1P-2S1D',
'2R-CRo': 'RM-1P-2S1D',
'LDST-3R': 'LDSTRM-2P-3S',
'LDST-3R-CRo': 'LDSTRM-2P-3S', # st*x
'LDST-3R-1W': 'LDSTRM-2P-2S1D', # st*x
+ 'LDST-2R': 'non-SV', # dcbz -- TODO: any vectorizable?
+ 'CRo': 'non-SV', # mtfsb1 -- TODO: any vectorizable?
}
print("# map to old SV Prefix")
print('')
condition = row[3]
insn = insns[(insn_name, condition)]
+ #if insn_name == 'rlwinm':
+ # print ("upd rlwinm", insn)
+
# start constructing svp64 CSV row
res = OrderedDict()
res['insn'] = insn_name