got sv.bc working for pospopcount

[openpower-isa.git] / src / openpower / sv / svstate.py

diff --git a/src/openpower/sv/svstate.py b/src/openpower/sv/svstate.py
index 9d593e182f34a7d7a243d576cdac1b8696a4fff6..eb65aa5f58f5404c289c13a2b0a85903cfc1813e 100644 (file)
--- a/src/openpower/sv/svstate.py
+++ b/src/openpower/sv/svstate.py
@@ -11,22 +11,47 @@ https://libre-soc.org/openpower/sv/sprs/
 | 7:13  |    vl    | Vector Length         |
 | 14:20 | srcstep  | for srcstep = 0..VL-1 |
 | 21:27 | dststep  | for dststep = 0..VL-1 |
-| 28:29 | subvl    | Sub-vector length     |
-| 30:31 | svstep   | for svstep = 0..SUBVL-1  |
+| 28:29 | dsubstep | for dsubstep = 0..SUBVL-1  |
+| 30:31 | ssubstep | for ssubstep = 0..SUBVL-1  |
+| 32:33 | mi0      | REMAP RA SVSHAPE0-3    |
+| 34:35 | mi1      | REMAP RB SVSHAPE0-3    |
+| 36:37 | mi2      | REMAP RC SVSHAPE0-3    |
+| 38:39 | mo0      | REMAP RT SVSHAPE0-3    |
+| 40:41 | mo1      | REMAP EA SVSHAPE0-3    |
+| 42:46 | SVme     | REMAP enable (RA-RT)  |
+| 47:52 | rsvd     | reserved              |
+| 53    | pack     | PACK (srcstrp reorder)  |
+| 54    | unpack   | UNPACK (dststep order)  |
+| 55:61 | hphint   | Horizontal Hint       |
+| 62    | RMpst    | REMAP persistence     |
+| 63    | vfirst   | Vertical First mode   |
 """
 
-from nmutil.iocontrol import RecordObject
-from nmigen import Signal
+from nmigen import Signal, Record
 
 
 # In nMigen, Record order is from LSB to MSB
-class SVSTATERec(RecordObject):
+# but Power ISA specs are all MSB to LSB (MSB0).
+class SVSTATERec(Record):
+    layout = [("vfirst", 1),
+            ("RMpst", 1),
+            ("hphint", 7),
+            ("unpack", 1),
+            ("pack", 1),
+            ("rsvd", 6),
+            ("SVme", 5),
+            ("mo1", 2),
+            ("mo0", 2),
+            ("mi2", 2),
+            ("mi1", 2),
+            ("mi0", 2),
+            ("ssubstep", 2),
+            ("dsubstep", 2),
+            ("dststep", 7),
+            ("srcstep", 7),
+            ("vl", 7),
+            ("maxvl", 7),
+        ]
+
     def __init__(self, name=None):
-        super().__init__(name=name)
-        self.rsvd = Signal(32) # TODO
-        self.svstep = Signal(2)
-        self.subvl = Signal(2)
-        self.dststep = Signal(7)
-        self.srcstep = Signal(7)
-        self.vl = Signal(7)
-        self.maxvl = Signal(7)
+        super().__init__(name=name, layout=SVSTATERec.layout)