add extra "persistence" bit to svremap instruction

[openpower-isa.git] / src / openpower / sv / trans / svp64.py

diff --git a/src/openpower/sv/trans/svp64.py b/src/openpower/sv/trans/svp64.py
index beef6a4d206ed021133f76b7368ff3f5ef9a8931..6ea5009af1b316595a20e5910b3f6e15ffcbc482 100644 (file)
--- a/src/openpower/sv/trans/svp64.py
+++ b/src/openpower/sv/trans/svp64.py
@@ -181,14 +181,16 @@ class SVP64Asm:
         log ("opcode, fields substed", ls, opcode, fields)
 
         # sigh have to do setvl here manually for now...
+        # note the subtract one from SVi.
         if opcode in ["setvl", "setvl."]:
             insn = 22 << (31-5)          # opcode 22, bits 0-5
             fields = list(map(int, fields))
             insn |= fields[0] << (31-10) # RT       , bits 6-10
             insn |= fields[1] << (31-15) # RA       , bits 11-15
-            insn |= fields[2] << (31-23) # SVi      , bits 16-23
-            insn |= fields[3] << (31-24) # vs       , bit  24
-            insn |= fields[4] << (31-25) # ms       , bit  25
+            insn |= (fields[2]-1) << (31-22) # SVi      , bits 16-22
+            insn |= fields[3] << (31-25) # ms       , bit  25
+            insn |= fields[4] << (31-24) # vs       , bit  24
+            insn |= fields[5] << (31-23) # vf       , bit  23
             insn |= 0b00000   << (31-30) # XO       , bits 26..30
             if opcode == 'setvl.':
                 insn |= 1 << (31-31)     # Rc=1     , bit 31
@@ -196,15 +198,34 @@ class SVP64Asm:
             yield ".long 0x%x" % insn
             return
 
-        # and svremap.  note that the dimension fields one subtracted from each
-        if opcode == 'svremap':
+        # and svshape.  note that the dimension fields one subtracted from each
+        if opcode == 'svshape':
             insn = 22 << (31-5)          # opcode 22, bits 0-5
             fields = list(map(int, fields))
             insn |= (fields[0]-1) << (31-10) # SVxd       , bits 6-10
             insn |= (fields[1]-1) << (31-15) # SVyd       , bits 11-15
             insn |= (fields[2]-1) << (31-20) # SVzd       , bits 16-20
-            insn |= (fields[3])   << (31-25) # SVRM       , bits 21-25
+            insn |= (fields[3])   << (31-24) # SVRM       , bits 21-24
+            insn |= (fields[4])   << (31-25) # vf         , bits 25
             insn |= 0b00001   << (31-30) # XO       , bits 26..30
+            #insn &= ((1<<32)-1)
+            log ("svshape", bin(insn))
+            yield ".long 0x%x" % insn
+            return
+
+        # and svremap
+        if opcode == 'svremap':
+            insn = 22 << (31-5)          # opcode 22, bits 0-5
+            fields = list(map(int, fields))
+            insn |= fields[0] << (31-10) # SVme       , bits 6-10
+            insn |= fields[1] << (31-12) # mi0        , bits 11-12
+            insn |= fields[2] << (31-14) # mi1        , bits 13-14
+            insn |= fields[3] << (31-16) # mi2        , bits 15-16
+            insn |= fields[4] << (31-18) # m00        , bits 17-18
+            insn |= fields[5] << (31-20) # m01        , bits 19-20
+            insn |= fields[6] << (31-21) # m01        , bit 21
+            insn |= 0b00010   << (31-30) # XO       , bits 26..30
+            #insn &= ((1<<32)-1)
             log ("svremap", bin(insn))
             yield ".long 0x%x" % insn
             return
@@ -811,7 +832,17 @@ class SVP64Asm:
             opcode |= int(v30b_newfields[1]) << (32-16) # FRA
             opcode |= int(v30b_newfields[2]) << (32-21) # FRB
             opcode |= int(v30b_newfields[3]) << (32-26) # FRC
-            opcode |= 5 << (32-31)   # bits 26-30
+            opcode |= 0b00101 << (32-31)   # bits 26-30
+            if rc:
+                opcode |= 1  # Rc, bit 31.
+            yield ".long 0x%x" % opcode
+        # argh, sv.ffadds etc. need to be done manually
+        elif v30b_op == 'ffadds':
+            opcode = 59 << (32-6)    # bits 0..6 (MSB0)
+            opcode |= int(v30b_newfields[0]) << (32-11) # FRT
+            opcode |= int(v30b_newfields[1]) << (32-16) # FRA
+            opcode |= int(v30b_newfields[2]) << (32-21) # FRB
+            opcode |= 0b01101 << (32-31)   # bits 26-30
             if rc:
                 opcode |= 1  # Rc, bit 31.
             yield ".long 0x%x" % opcode
@@ -904,7 +935,7 @@ def asm_process():
         ls = line.split("#")
         # identify macros
         op = ls[0].strip()
-        if op.startswith("setvl") or op.startswith("svremap"):
+        if op.startswith("setvl") or op.startswith("svshape"):
             ws, line = get_ws(ls[0])
             lst = list(isa.translate_one(ls[0].strip(), macros))
             lst = '; '.join(lst)
@@ -949,7 +980,7 @@ if __name__ == '__main__':
     lst += [
                  'sv.stw 5.v, 4(1.v)',
                  'sv.ld 5.v, 4(1.v)',
-                 'setvl. 2, 3, 4, 1, 1',
+                 'setvl. 2, 3, 4, 0, 1, 1',
           ]
     lst = [
             "sv.stfsu 0.v, 16(4.v)",
@@ -967,8 +998,14 @@ if __name__ == '__main__':
              #'sv.lhzbr 5.v, 11(9.v), 15',
              #'sv.lwzbr 5.v, 11(9.v), 15',
              'sv.ffmadds 6.v, 2.v, 4.v, 6.v',
-             'svremap 2, 2, 3, 0',
     ]
+    lst = [
+             #'sv.fmadds 0.v, 8.v, 16.v, 4.v',
+             #'sv.ffadds 0.v, 8.v, 4.v',
+             'svremap 11, 0, 1, 2, 3, 2, 1',
+             'svshape 8, 1, 1, 1, 0',
+             'svshape 8, 1, 1, 1, 1',
+            ]
     isa = SVP64Asm(lst, macros=macros)
     print ("list", list(isa))
     csvs = SVP64RM()