power_insn: support verbosity levels

[openpower-isa.git] / src / openpower / sv / trans / svp64.py

diff --git a/src/openpower/sv/trans/svp64.py b/src/openpower/sv/trans/svp64.py
index 7d32cf7cdec69c61e970512885d60a72c8b9905b..7b146fb4ca2a4170abb69f7d4bfcddfe96abc0fa 100644 (file)
--- a/src/openpower/sv/trans/svp64.py
+++ b/src/openpower/sv/trans/svp64.py
@@ -173,7 +173,7 @@ def svshape(fields):
     SVzd -= 1
 
     # check SVrm for reserved (and svshape2) values
-    assert SVrm not in [0b0111, 0b1000, 0b1001], \
+    assert SVrm not in [0b1000, 0b1001], \
             "svshape reserved SVrm value %s" % bin(SVrm)
 
     return instruction(
@@ -197,11 +197,11 @@ def svshape2(fields):
 
     https://libre-soc.org/openpower/sv/remap/discussion
 
-    * svshape2 offs,yx,rmm,SVd,sk,mm
+    * svshape2 SVo,SVM2yx,rmm,SVd,sk,mm
 
     # 1.6.35.1 SVM2-FORM from fields.txt
-    # |0     |6     |10|11      |16    |21 |24|25 |26    |31  |
-    # | PO   | offs |yx|   rmm  | SVd  |XO |mm|sk |   XO      |
+    # |0     |6     |10   |11      |16    |21 |24|25 |26    |31  |
+    # | PO   | SVo  |SVMyx|   rmm  | SVd  |XO |mm|sk |   XO      |
 
     note that this fits into the space of svshape and that XO is
     split across 2 areas.
@@ -325,7 +325,7 @@ def fsins(fields, Rc):
     # |0     |6 |7|8|9  |10  |11|12|13  |15|16|17     |20|21    |31  |
     # | PO   |   FRT         |     ///     |   FRB       |   XO |Rc  |
     PO = 59
-    XO = 0b1000001110
+    XO = 0b1001001101
     (FRT, FRB) = fields
     return instruction(
         (PO, 0, 5),
@@ -348,7 +348,7 @@ def fcoss(fields, Rc):
     # |0     |6 |7|8|9  |10  |11|12|13  |15|16|17     |20|21    |31  |
     # | PO   |   FRT         |     ///     |   FRB       |   XO |Rc  |
     PO = 59
-    XO = 0b1000101110
+    XO = 0b1001101100
     (FRT, FRB) = fields
     return instruction(
         (PO, 0, 5),
@@ -630,7 +630,7 @@ def decode_imm(field):
         return None, field
 
 
-def crf_extra(etype, regmode, field, extras):
+def crf_extra(etype, rname, extra_idx, regmode, field, extras):
     """takes a CR Field number (CR0-CR127), splits into EXTRA2/3 and v3.0
     the scalar/vector mode (crNN.v or crNN.s) changes both the format
     of the EXTRA2/3 encoding as well as what range of registers is possible.
@@ -684,6 +684,9 @@ def to_number(field):
     return int(field)
 
 
+db = Database(find_wiki_dir())
+
+
 # decodes svp64 assembly listings and creates EXT001 svp64 prefixes
 class SVP64Asm:
     def __init__(self, lst, bigendian=False, macros=None):
@@ -880,7 +883,8 @@ class SVP64Asm:
             # encode SV-CR 3-bit field into extra, v3.0field.
             # 3-bit is for things like BF and BFA
             elif rtype == 'CR_3bit':
-                sv_extra, field = crf_extra(etype, regmode, field, extras)
+                sv_extra, field = crf_extra(etype, rname, extra_idx,
+                                            regmode, field, extras)
 
             # encode SV-CR 5-bit field into extra, v3.0field
             # 5-bit is for things like BA BB BC BT etc.
@@ -890,7 +894,8 @@ class SVP64Asm:
                 cr_subfield = field & 0b11  # record bottom 2 bits for later
                 field = field >> 2         # strip bottom 2 bits
                 # use the exact same 3-bit function for the top 3 bits
-                sv_extra, field = crf_extra(etype, regmode, field, extras)
+                sv_extra, field = crf_extra(etype, rname, extra_idx,
+                                            regmode, field, extras)
                 # reconstruct the actual 5-bit CR field (preserving the
                 # bottom 2 bits, unaltered)
                 field = (field << 2) | cr_subfield
@@ -917,7 +922,6 @@ class SVP64Asm:
         log("extras", extras)
 
         # rright. now we have all the info. start creating SVP64 instruction.
-        db = Database(find_wiki_dir())
         svp64_insn = SVP64Instruction.pair(prefix=0, suffix=0)
         svp64_prefix = svp64_insn.prefix
         svp64_rm = svp64_insn.prefix.rm
@@ -1155,15 +1159,17 @@ class SVP64Asm:
         """
             | 0-1 |  2  |  3   4  |  description              |
             | --- | --- |---------|-------------------------- |
-            | 00  |   0 |  dz  sz | normal mode                      |
+            | 00  |   0 |  dz  sz | simple mode                      |
             | 00  |   1 | 0  RG   | scalar reduce mode (mapreduce), SUBVL=1 |
-            | 00  |   1 | 1  /    | parallel reduce mode (mapreduce), SUBVL=1 |
-            | 00  |   1 | SVM RG  | subvector reduce mode, SUBVL>1   |
+            | 00  |   1 | SVM 0   | subvector reduce mode, SUBVL>1   |
+            | 00  |   1 | SVM 1   | Pack/Unpack mode, SUBVL>1   |
             | 01  | inv | CR-bit  | Rc=1: ffirst CR sel              |
             | 01  | inv | VLi RC1 |  Rc=0: ffirst z/nonz |
-            | 10  |   N | dz   sz |  sat mode: N=0/1 u/s |
+            | 10  |   N | dz   sz |  sat mode: N=0/1 u/s, SUBVL=1 |
+            | 10  |   N | zz   0  |  sat mode: N=0/1 u/s, SUBVL>1 |
+            | 10  |   N | zz   1  |  Pack/Unpack sat mode: N=0/1 u/s, SUBVL>1 |
             | 11  | inv | CR-bit  |  Rc=1: pred-result CR sel |
-            | 11  | inv | dz  RC1 |  Rc=0: pred-result z/nonz |
+            | 11  | inv | zz  RC1 |  Rc=0: pred-result z/nonz |
         """
 
         # https://libre-soc.org/openpower/sv/ldst/