from openpower.simulator.program import Program
from openpower.sv.trans.pysvp64dis import load, dump
from openpower.sv.trans.svp64 import SVP64Asm
-from openpower.decoder.power_insn import Verbosity
+from openpower.decoder.power_insn import Database, Verbosity
+from openpower.decoder.power_enums import find_wiki_dir
+from openpower.sv import sv_binutils_fptrans
import unittest
import sys
print ("insns", insns)
for i, line in enumerate(dump(insns, verbosity=Verbosity.SHORT)):
name = expected[i].split(" ")[0]
- with self.subTest(name):
+ with self.subTest("%d:%s" % (i, name)):
print("instruction", repr(line), repr(expected[i]))
self.assertEqual(expected[i], line,
"instruction does not match "
"'%s' expected '%s'" % (line, expected[i]))
- def test_0_addi(self):
+ def test_0_add(self):
expected = ['addi 1,5,2',
+ 'add 1,5,2',
+ 'add. 1,5,2',
+ 'addo 1,5,2',
+ 'addo. 1,5,2',
]
self._do_tst(expected)
'sv.isel 12,2,3,*33',
'sv.isel 12,2,3,*483',
'sv.isel 12,2,3,63',
+ 'sv.isel 12,2,3,*99',
]
self._do_tst(expected)
]
self._do_tst(expected)
+ def test_5_setvl(self):
+ expected = [
+ "setvl 5,4,5,0,1,1",
+ "setvl. 5,4,5,0,1,1",
+ ]
+ self._do_tst(expected)
+
+ def test_6_sv_setvl(self):
+ expected = [
+ "sv.setvl 5,4,5,0,1,1",
+ "sv.setvl 63,35,5,0,1,1",
+ ]
+ self._do_tst(expected)
+
+ def test_7_batch(self):
+ "these come from https://bugs.libre-soc.org/show_bug.cgi?id=917#c25"
+ expected = [
+ "addi 2,2,0",
+ "addis 9,2,0",
+ "addi 9,9,0",
+ "rlwinm 7,7,2,0,29",
+ "mulli 0,7,31",
+ "add 10,6,0",
+ "setvl 0,0,8,1,1,0",
+ "addi 16,4,124",
+ "lfiwax 0,0,5",
+ "addi 5,3,64",
+ "sv.lfs *32,256(4)",
+ "sv.lfs *40,256(5)",
+ "sv.fmuls *32,*32,*40",
+ "sv.fadds 0,*32,0",
+ "addi 5,3,192",
+ "addi 4,4,128",
+ "sv.lfs *32,256(4)",
+ "sv.lfs *40,256(5)",
+ "sv.fmuls *32,*32,*40",
+ "sv.fsubs 0,0,*32",
+ "addi 4,4,-128",
+ "stfs 0,0(6)",
+ "add 6,6,7",
+ "addi 4,4,4",
+ "addi 0,0,15",
+ "mtspr 288,0",
+ "addi 8,0,4",
+ "lfiwax 0,0,9",
+ "lfiwax 1,0,9",
+ "addi 5,3,64",
+ "add 5,5,8",
+ "sv.lfs *32,256(5)",
+ "sv.lfs *40,256(4)",
+ "sv.lfs *48,256(16)",
+ "sv.fmuls *40,*32,*40",
+ "sv.fadds 0,0,*40",
+ "sv.fmuls *32,*32,*48",
+ "sv.fsubs 1,1,*32",
+ "addi 5,3,192",
+ "subf 5,8,5",
+ "addi 4,4,128",
+ "addi 16,16,128",
+ "sv.lfs *32,256(5)",
+ "sv.lfs *40,256(4)",
+ "sv.lfs *48,256(16)",
+ "sv.fmuls *40,*32,*40",
+ "sv.fsubs 0,0,*40",
+ "sv.fmuls *32,*32,*48",
+ "sv.fsubs 1,1,*32",
+ "addi 4,4,-128",
+ "addi 16,16,-128",
+ "stfs 0,0(6)",
+ "add 6,6,7",
+ "stfs 1,0(10)",
+ "subf 10,7,10",
+ "addi 8,8,4",
+ "addi 4,4,4",
+ "addi 16,16,-4",
+ "bc 16,0,-0xb4",
+ "addi 5,3,128",
+ "addi 4,4,128",
+ "lfiwax 0,0,9",
+ "sv.lfs *32,256(4)",
+ "sv.lfs *40,256(5)",
+ "sv.fmuls *32,*32,*40",
+ "sv.fsubs 0,0,*32",
+ "stfs 0,0(6)",
+ "bclr 20,0,0",
+ ]
+ self._do_tst(expected)
+
+ def test_8_madd(self):
+ expected = [
+ "maddhd 5,4,5,3",
+ "maddhdu 5,4,5,3",
+ "maddld 5,4,5,3",
+ ]
+ self._do_tst(expected)
+
+ def test_9_fptrans(self):
+ "enumerates a list of fptrans instruction disassembly entries"
+ db = Database(find_wiki_dir())
+ entries = sorted(sv_binutils_fptrans.collect(db))
+ dis = lambda entry: sv_binutils_fptrans.dis(entry, binutils=False)
+ self._do_tst(list(map(dis, entries)))
+
+ def test_10_vec(self):
+ expected = [
+ "sv.add./vec2 *3,*7,*11",
+ "sv.add./vec3 *3,*7,*11",
+ "sv.add./vec4 *3,*7,*11",
+ ]
+ self._do_tst(expected)
+
+ def test_11_elwidth(self):
+ expected = [
+ "sv.add./dw=8 *3,*7,*11",
+ "sv.add./dw=16 *3,*7,*11",
+ "sv.add./dw=32 *3,*7,*11",
+ "sv.add./sw=8 *3,*7,*11",
+ "sv.add./sw=16 *3,*7,*11",
+ "sv.add./sw=32 *3,*7,*11",
+ "sv.add./dw=8/sw=16 *3,*7,*11",
+ "sv.add./dw=16/sw=32 *3,*7,*11",
+ "sv.add./dw=32/sw=8 *3,*7,*11",
+ "sv.add./w=32 *3,*7,*11",
+ "sv.add./w=8 *3,*7,*11",
+ "sv.add./w=16 *3,*7,*11",
+ ]
+ self._do_tst(expected)
+
+ def test_12_sat(self):
+ expected = [
+ "sv.add./satu *3,*7,*11",
+ "sv.add./sats *3,*7,*11",
+ ]
+ self._do_tst(expected)
+
+ def test_12_mr_r(self):
+ expected = [
+ "sv.add./mrr/vec2 *3,*7,*11",
+ "sv.add./mr/vec2 *3,*7,*11",
+ "sv.add./mrr *3,*7,*11",
+ "sv.add./mr *3,*7,*11",
+ ]
+ self._do_tst(expected)
+
+ def test_13_RC1(self):
+ expected = [
+ "sv.add/ff=RC1 *3,*7,*11",
+ "sv.add/pr=RC1 *3,*7,*11",
+ "sv.add/ff=~RC1 *3,*7,*11",
+ "sv.add/pr=~RC1 *3,*7,*11",
+ ]
+ self._do_tst(expected)
+
+ def test_14_rc1_ff_pr(self):
+ expected = [
+ "sv.add./ff=eq *3,*7,*11",
+ "sv.add./ff=ns *3,*7,*11",
+ "sv.add./pr=eq *3,*7,*11",
+ "sv.add./pr=ns *3,*7,*11",
+ ]
+ self._do_tst(expected)
+
+ def test_15_predicates(self):
+ expected = [
+ "sv.add./m=r3 *3,*7,*11",
+ "sv.add./m=1<<r3 *3,*7,*11",
+ "sv.add./m=~r10 *3,*7,*11",
+ "sv.add./m=so *3,*7,*11",
+ "sv.add./m=ne *3,*7,*11",
+ "sv.add./m=lt *3,*7,*11",
+ "sv.add. *3,*7,*11",
+ "sv.extsw/m=r30 3,7",
+ "sv.extsw/sm=r30/dm=~r30 3,7",
+ "sv.extsw/sm=gt/dm=eq 3,7",
+ "sv.extsw/sm=~r3 3,7",
+ "sv.extsw/dm=r30 3,7",
+ ]
+ self._do_tst(expected)
+
+ def test_15_els(self):
+ expected = [
+ "sv.stw/els *4,16(2)",
+ "sv.lfs/els *1,256(4)",
+ ]
+ self._do_tst(expected)
+
+ def test_16_bc(self):
+ # hilarious. this should be autogenerated from a sequence
+ # of lists of options. it's a lot of frickin options.
+ expected = [
+ "sv.bc/all 12,*1,0xc",
+ "sv.bc/snz 12,*1,0xc",
+ "sv.bc/all/sl/slu 12,*1,0xc",
+ "sv.bc/all/snz/sl/slu/lru 12,*1,0xc",
+ "sv.bc/vs/all/snz/sl/slu/lru 12,*1,0xc",
+ "sv.bc/vsi/all/snz/sl/slu/lru 12,*1,0xc",
+ "sv.bc/vsb/all/snz/sl/slu/lru 12,*1,0xc",
+ "sv.bc/vsbi/all/snz/sl/slu/lru 12,*1,0xc",
+ "sv.bc/ctr/all/snz/sl/slu/lru 12,*1,0xc",
+ "sv.bc/cti/all/snz/sl/slu/lru 12,*1,0xc",
+ "sv.bc/vsb/ctr/all/snz/sl/slu/lru 12,*1,0xc",
+ ]
+ self._do_tst(expected)
+
if __name__ == "__main__":
unittest.main()
projects / openpower-isa.git / blobdiff