add sv.bc/ctr/vsb unit test to test_pysvp64dis.py to show it is possible

[openpower-isa.git] / src / openpower / sv / trans / test_pysvp64dis.py

diff --git a/src/openpower/sv/trans/test_pysvp64dis.py b/src/openpower/sv/trans/test_pysvp64dis.py
index 981147e14c70d08e4484587e45c94800ae9ebfda..98173ba566b6f2e475d36c2a2a2186af095bf8a6 100644 (file)
--- a/src/openpower/sv/trans/test_pysvp64dis.py
+++ b/src/openpower/sv/trans/test_pysvp64dis.py
@@ -256,6 +256,8 @@ class SVSTATETestCase(unittest.TestCase):
         self._do_tst(expected)
 
     def test_16_bc(self):
+        # hilarious. this should be autogenerated from a sequence
+        # of lists of options. it's a lot of frickin options.
         expected = [
                     "sv.bc/all 12,*1,0xc",
                     "sv.bc/snz 12,*1,0xc",
@@ -267,6 +269,7 @@ class SVSTATETestCase(unittest.TestCase):
                     "sv.bc/vsbi/all/snz/sl/slu/lru 12,*1,0xc",
                     "sv.bc/ctr/all/snz/sl/slu/lru 12,*1,0xc",
                     "sv.bc/cti/all/snz/sl/slu/lru 12,*1,0xc",
+                    "sv.bc/vsb/ctr/all/snz/sl/slu/lru 12,*1,0xc",
                         ]
         self._do_tst(expected)