add sv.bc/ctr/vsb unit test to test_pysvp64dis.py to show it is possible

[openpower-isa.git] / src / openpower / sv / trans / test_pysvp64dis.py

diff --git a/src/openpower/sv/trans/test_pysvp64dis.py b/src/openpower/sv/trans/test_pysvp64dis.py
index a96e5a13da21fe09f69c6a37c1bf1cf5107245ed..98173ba566b6f2e475d36c2a2a2186af095bf8a6 100644 (file)
--- a/src/openpower/sv/trans/test_pysvp64dis.py
+++ b/src/openpower/sv/trans/test_pysvp64dis.py
@@ -182,9 +182,94 @@ class SVSTATETestCase(unittest.TestCase):
 
     def test_11_elwidth(self):
         expected = [
-                    "sv.add./ew=8 *3,*7,*11",
-                    "sv.add./ew=16 *3,*7,*11",
-                    "sv.add./ew=32 *3,*7,*11",
+                    "sv.add./dw=8 *3,*7,*11",
+                    "sv.add./dw=16 *3,*7,*11",
+                    "sv.add./dw=32 *3,*7,*11",
+                    "sv.add./sw=8 *3,*7,*11",
+                    "sv.add./sw=16 *3,*7,*11",
+                    "sv.add./sw=32 *3,*7,*11",
+                    "sv.add./dw=8/sw=16 *3,*7,*11",
+                    "sv.add./dw=16/sw=32 *3,*7,*11",
+                    "sv.add./dw=32/sw=8 *3,*7,*11",
+                    "sv.add./w=32 *3,*7,*11",
+                    "sv.add./w=8 *3,*7,*11",
+                    "sv.add./w=16 *3,*7,*11",
+                        ]
+        self._do_tst(expected)
+
+    def test_12_sat(self):
+        expected = [
+                    "sv.add./satu *3,*7,*11",
+                    "sv.add./sats *3,*7,*11",
+                        ]
+        self._do_tst(expected)
+
+    def test_12_mr_r(self):
+        expected = [
+                    "sv.add./mrr/vec2 *3,*7,*11",
+                    "sv.add./mr/vec2 *3,*7,*11",
+                    "sv.add./mrr *3,*7,*11",
+                    "sv.add./mr *3,*7,*11",
+                        ]
+        self._do_tst(expected)
+
+    def test_13_RC1(self):
+        expected = [
+                    "sv.add/ff=RC1 *3,*7,*11",
+                    "sv.add/pr=RC1 *3,*7,*11",
+                    "sv.add/ff=~RC1 *3,*7,*11",
+                    "sv.add/pr=~RC1 *3,*7,*11",
+                        ]
+        self._do_tst(expected)
+
+    def test_14_rc1_ff_pr(self):
+        expected = [
+                    "sv.add./ff=eq *3,*7,*11",
+                    "sv.add./ff=ns *3,*7,*11",
+                    "sv.add./pr=eq *3,*7,*11",
+                    "sv.add./pr=ns *3,*7,*11",
+                        ]
+        self._do_tst(expected)
+
+    def test_15_predicates(self):
+        expected = [
+                    "sv.add./m=r3 *3,*7,*11",
+                    "sv.add./m=1<<r3 *3,*7,*11",
+                    "sv.add./m=~r10 *3,*7,*11",
+                    "sv.add./m=so *3,*7,*11",
+                    "sv.add./m=ne *3,*7,*11",
+                    "sv.add./m=lt *3,*7,*11",
+                    "sv.add. *3,*7,*11",
+                    "sv.extsw/m=r30 3,7",
+                    "sv.extsw/sm=r30/dm=~r30 3,7",
+                    "sv.extsw/sm=gt/dm=eq 3,7",
+                    "sv.extsw/sm=~r3 3,7",
+                    "sv.extsw/dm=r30 3,7",
+                        ]
+        self._do_tst(expected)
+
+    def test_15_els(self):
+        expected = [
+                    "sv.stw/els *4,16(2)",
+                    "sv.lfs/els *1,256(4)",
+                        ]
+        self._do_tst(expected)
+
+    def test_16_bc(self):
+        # hilarious. this should be autogenerated from a sequence
+        # of lists of options. it's a lot of frickin options.
+        expected = [
+                    "sv.bc/all 12,*1,0xc",
+                    "sv.bc/snz 12,*1,0xc",
+                    "sv.bc/all/sl/slu 12,*1,0xc",
+                    "sv.bc/all/snz/sl/slu/lru 12,*1,0xc",
+                    "sv.bc/vs/all/snz/sl/slu/lru 12,*1,0xc",
+                    "sv.bc/vsi/all/snz/sl/slu/lru 12,*1,0xc",
+                    "sv.bc/vsb/all/snz/sl/slu/lru 12,*1,0xc",
+                    "sv.bc/vsbi/all/snz/sl/slu/lru 12,*1,0xc",
+                    "sv.bc/ctr/all/snz/sl/slu/lru 12,*1,0xc",
+                    "sv.bc/cti/all/snz/sl/slu/lru 12,*1,0xc",
+                    "sv.bc/vsb/ctr/all/snz/sl/slu/lru 12,*1,0xc",
                         ]
         self._do_tst(expected)