insndb: rename types into core

[openpower-isa.git] / src / openpower / sv / trans / test_pysvp64dis.py

diff --git a/src/openpower/sv/trans/test_pysvp64dis.py b/src/openpower/sv/trans/test_pysvp64dis.py
index ed1743242523856b5d459aefaaa3a1499e97772f..c17117eb13f0cbc965f70e855395affb2ff2ad12 100644 (file)
--- a/src/openpower/sv/trans/test_pysvp64dis.py
+++ b/src/openpower/sv/trans/test_pysvp64dis.py
@@ -1,7 +1,7 @@
 from openpower.simulator.program import Program
-from openpower.sv.trans.pysvp64dis import load, dump
-from openpower.sv.trans.svp64 import SVP64Asm
-from openpower.decoder.power_insn import Database, Style
+from openpower.insndb.dis import load, dump
+from openpower.insndb.asm import SVP64Asm
+from openpower.insndb.core import Database, Style
 from openpower.decoder.power_enums import find_wiki_dir
 from openpower.sv import sv_binutils_fptrans
 import unittest
@@ -72,7 +72,7 @@ class SVSTATETestCase(unittest.TestCase):
         expected = [
                     'sv.crand *16,*2,*33',
                     'sv.crand 12,2,33',
-                    'sv.crand/ff=eq/m=r10 12,2,33',
+                    'sv.crand/ff=RC1/m=r10 12,2,33',
                     'sv.crand/m=r10 12,2,33',
                     'sv.crand/m=r10/sz 12,2,33',
                     'sv.crand/m=r10/zz 12,2,33',    # SHOULD PASS
@@ -230,9 +230,7 @@ class SVSTATETestCase(unittest.TestCase):
     def test_13_RC1(self):
         expected = [
                     "sv.add/ff=RC1 *3,*7,*11",
-                    "sv.add/pr=RC1 *3,*7,*11",
                     "sv.add/ff=~RC1 *3,*7,*11",
-                    "sv.add/pr=~RC1 *3,*7,*11",
                         ]
         self._do_tst(expected)
 
@@ -245,8 +243,6 @@ class SVSTATETestCase(unittest.TestCase):
                     "sv.add./ff=le *3,*7,*11",
                     "sv.add./ff=gt *3,*7,*11",
                     "sv.add./ff=ne *3,*7,*11",
-                    "sv.add./pr=eq *3,*7,*11",
-                    "sv.add./pr=ns *3,*7,*11",
                         ]
         self._do_tst(expected)
 
@@ -304,6 +300,7 @@ class SVSTATETestCase(unittest.TestCase):
     def test_18_sea(self):
         expected = [
                     "sv.ldux/sea 5,6,7",
+                    "sv.ldux/pi/sea 5,6,7",
                         ]
         self._do_tst(expected)
 
@@ -319,12 +316,13 @@ class SVSTATETestCase(unittest.TestCase):
     def test_20_cmp(self):
         expected = [
                     "sv.cmp *4,1,*0,1",
-                    "sv.cmp/ff=RC1 *4,1,*0,1",
-                    "sv.cmp/ff=RC1/vli *4,1,*0,1",
-                    "sv.cmp/ff=~RC1 *4,1,*0,1",
-                    "sv.cmp/ff=RC1/m=r3/sz *4,1,*0,1",
-                    "sv.cmp/dz/ff=RC1/m=r3 *4,1,*0,1",
-                    "sv.cmp/dz/ff=RC1/m=r3/sz *4,1,*0,1",
+                    "sv.cmp/ff=eq *4,1,*0,1",
+                    "sv.cmp/ff=eq/vli *4,1,*0,1",
+                    "sv.cmp/ff=ne *4,1,*0,1",
+                    "sv.cmp/ff=eq/m=r3/zz *4,1,*0,1",
+                    "sv.cmp/ff=lt/m=r3/zz *4,1,*0,1",
+                    "sv.cmp/ff=gt/m=r3/zz *4,1,*0,1",
+                    "sv.cmp/zz/ff=gt/m=r3 *4,1,*0,1", # WRONG
                         ]
         self._do_tst(expected)
 
@@ -424,24 +422,32 @@ class SVSTATETestCase(unittest.TestCase):
                         ]
         self._do_tst(expected)
 
-    def test_31_shadd_shadduw(self):
-        expected = [
-                    "shadd 31,0,0,0",
-                    "shadd 0,31,0,0",
-                    "shadd 0,0,31,0",
-                    "shadd 0,0,0,3",
-                    "shadd. 31,0,0,0",
-                    "shadd. 0,31,0,0",
-                    "shadd. 0,0,31,0",
-                    "shadd. 0,0,0,3",
-                    "shadduw 31,0,0,0",
-                    "shadduw 0,31,0,0",
-                    "shadduw 0,0,31,0",
-                    "shadduw 0,0,0,3",
-                    "shadduw. 31,0,0,0",
-                    "shadduw. 0,31,0,0",
-                    "shadduw. 0,0,31,0",
-                    "shadduw. 0,0,0,3",
+    def test_31_sadd_saddw_sadduw(self):
+        expected = [
+                    "sadd 31,0,0,0",
+                    "sadd 0,31,0,0",
+                    "sadd 0,0,31,0",
+                    "sadd 0,0,0,3",
+                    "sadd. 31,0,0,0",
+                    "sadd. 0,31,0,0",
+                    "sadd. 0,0,31,0",
+                    "sadd. 0,0,0,3",
+                    "saddw 31,0,0,0",
+                    "saddw 0,31,0,0",
+                    "saddw 0,0,31,0",
+                    "saddw 0,0,0,3",
+                    "saddw. 31,0,0,0",
+                    "saddw. 0,31,0,0",
+                    "saddw. 0,0,31,0",
+                    "saddw. 0,0,0,3",
+                    "sadduw 31,0,0,0",
+                    "sadduw 0,31,0,0",
+                    "sadduw 0,0,31,0",
+                    "sadduw 0,0,0,3",
+                    "sadduw. 31,0,0,0",
+                    "sadduw. 0,31,0,0",
+                    "sadduw. 0,0,31,0",
+                    "sadduw. 0,0,0,3",
                         ]
         self._do_tst(expected)
 
@@ -463,5 +469,32 @@ class SVSTATETestCase(unittest.TestCase):
                         ]
         self._do_tst(expected)
 
+    def test_34_ldst_update_imm_ffirst(self):
+        expected = [
+                    "sv.ldu/ff=~RC1/vli *16,0(*17)",
+                        ]
+        self._do_tst(expected)
+
+    def test_35_ffmadds(self):
+        expected = [
+                    "sv.ffmadds *0,*0,*0",
+                        ]
+        self._do_tst(expected)
+
+    def test_36_extras_rlwimi(self):
+        self._do_tst(["sv.rlwimi 3, 1, 5, 20, 6"])
+
+    def test_36_extras_rlwimi_(self):
+        self._do_tst(["sv.rlwimi. 3, 1, 5, 20, 6"])
+
+    def test_36_extras_rldimi(self):
+        self._do_tst(["sv.rldimi 3, 4, 56, 4"])
+
+    def test_36_extras_rldimi_(self):
+        self._do_tst(["sv.rldimi. 3, 4, 56, 4"])
+
+    def test_36_extras_fishmv(self):
+        self._do_tst(["sv.fishmv 3, 0x0FD0"])
+
 if __name__ == "__main__":
     unittest.main()