add first bmask unit test

[openpower-isa.git] / src / openpower / test / bitmanip / av_cases.py

diff --git a/src/openpower/test/bitmanip/av_cases.py b/src/openpower/test/bitmanip/av_cases.py
index 2509613cfa5088732e77591f50d7c6afd97b21ed..b02bd5b241fab053bf3f83d9aeeeb1c53d0494ed 100644 (file)
--- a/src/openpower/test/bitmanip/av_cases.py
+++ b/src/openpower/test/bitmanip/av_cases.py
@@ -401,6 +401,7 @@ class AVTestCase(TestAccumulatorBase):
     def case_0_cprop(self):
         lst = ["cprop 3, 1, 2" ]
         lst = list(SVP64Asm(lst, bigendian))
+        last_pc = len(lst)*4
         reg_a = 0b000001
         reg_b = 0b000111
         reg_t = 0b001111
@@ -408,7 +409,7 @@ class AVTestCase(TestAccumulatorBase):
         initial_regs = [0] * 32
         initial_regs[1] = reg_a
         initial_regs[2] = reg_b
-        e = ExpectedState(pc=4)
+        e = ExpectedState(pc=last_pc)
         e.intregs[1] = reg_a
         e.intregs[2] = reg_b
         e.intregs[3] = reg_t
@@ -417,6 +418,7 @@ class AVTestCase(TestAccumulatorBase):
     def case_1_cprop(self):
         lst = ["cprop 3, 1, 2" ]
         lst = list(SVP64Asm(lst, bigendian))
+        last_pc = len(lst)*4
         reg_a = 0b000010
         reg_b = 0b001111
         reg_t = 0b011100
@@ -424,7 +426,7 @@ class AVTestCase(TestAccumulatorBase):
         initial_regs = [0] * 32
         initial_regs[1] = reg_a
         initial_regs[2] = reg_b
-        e = ExpectedState(pc=4)
+        e = ExpectedState(pc=last_pc)
         e.intregs[1] = reg_a
         e.intregs[2] = reg_b
         e.intregs[3] = reg_t
@@ -433,6 +435,7 @@ class AVTestCase(TestAccumulatorBase):
     def case_2_cprop(self):
         lst = ["cprop 3, 1, 2" ]
         lst = list(SVP64Asm(lst, bigendian))
+        last_pc = len(lst)*4
         reg_a = 0b000010
         reg_b = 0b001110
         reg_t = 0b011110
@@ -440,7 +443,32 @@ class AVTestCase(TestAccumulatorBase):
         initial_regs = [0] * 32
         initial_regs[1] = reg_a
         initial_regs[2] = reg_b
-        e = ExpectedState(pc=4)
+        e = ExpectedState(pc=last_pc)
+        e.intregs[1] = reg_a
+        e.intregs[2] = reg_b
+        e.intregs[3] = reg_t
+        self.add_case(Program(lst, bigendian), initial_regs, expected=e)
+
+    def case_0_bmask(self):
+        """
+        https://git.libre-soc.org/?p=libreriscv.git;a=blob;f=openpower/sv/bmask.py
+        https://git.libre-soc.org/?p=libreriscv.git;a=blob;f=openpower/sv/test_bmask.py
+        https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=openpower/isa/av.mdwn;hb=HEAD
+        SBF = 0b01010 # set before first
+        SOF = 0b01001 # set only first
+        SIF = 0b10000 # set including first 10011 also works no idea why yet
+        """
+        lst = ["bmask 3, 1, 2, 10, 0" ]
+        lst = list(SVP64Asm(lst, bigendian))
+        last_pc = len(lst)*4
+        reg_a = 0b10010100
+        reg_b = 0b11000011
+        reg_t = 0b01000011
+
+        initial_regs = [0] * 32
+        initial_regs[1] = reg_a
+        initial_regs[2] = reg_b
+        e = ExpectedState(pc=last_pc)
         e.intregs[1] = reg_a
         e.intregs[2] = reg_b
         e.intregs[3] = reg_t