projects / openpower-isa.git / blobdiff
? search:
summary | shortlog | log | commit | commitdiff | tree
raw | inline | side by side
add first bmask unit test
[openpower-isa.git] / src / openpower / test / bitmanip / av_cases.py
diff --git a/src/openpower/test/bitmanip/av_cases.py b/src/openpower/test/bitmanip/av_cases.py
index 6e689e9fd889a69f8af90aa4b79f987a517b5ae2..b02bd5b241fab053bf3f83d9aeeeb1c53d0494ed 100644 (file)
--- a/src/openpower/test/bitmanip/av_cases.py
+++ b/src/openpower/test/bitmanip/av_cases.py
@@ -165,8 +165,8 @@ class AVTestCase(TestAccumulatorBase):
         e = ExpectedState(pc=4)
         e.intregs[1] = 1
         e.intregs[2] = 0x8000_0000_0000_0000
-        e.intregs[3] = 0x8000_0000_0000_0000
-        e.crregs[0] = 0x8 # RT is -ve
+        e.intregs[3] = min(e.intregs[1], e.intregs[2])
+        e.crregs[0] = 0x4
         self.add_case(Program(lst, bigendian), initial_regs, expected=e)
 
     def case_0_avgadd(self):
@@ -221,6 +221,32 @@ class AVTestCase(TestAccumulatorBase):
         e.intregs[3] = 0xffffffffffffffff
         self.add_case(Program(lst, bigendian), initial_regs, expected=e)
 
+    def case_0_absds(self):
+        lst = ["absds 3, 1, 2"]
+        lst = list(SVP64Asm(lst, bigendian))
+
+        initial_regs = [0] * 32
+        initial_regs[1] = 0x1
+        initial_regs[2] = 0x2
+        e = ExpectedState(pc=4)
+        e.intregs[1] = 0x1
+        e.intregs[2] = 0x2
+        e.intregs[3] = 0x1
+        self.add_case(Program(lst, bigendian), initial_regs, expected=e)
+
+    def case_1_absds(self):
+        lst = ["absds 3, 1, 2"]
+        lst = list(SVP64Asm(lst, bigendian))
+
+        initial_regs = [0] * 32
+        initial_regs[1] = 0xffffffffffffffff
+        initial_regs[2] = 0x2
+        e = ExpectedState(pc=4)
+        e.intregs[1] = 0xffffffffffffffff
+        e.intregs[2] = 0x2
+        e.intregs[3] = 0x3
+        self.add_case(Program(lst, bigendian), initial_regs, expected=e)
+
     def case_0_absdu(self):
         lst = ["absdu 3, 1, 2"]
         lst = list(SVP64Asm(lst, bigendian))
@@ -244,7 +270,7 @@ class AVTestCase(TestAccumulatorBase):
         e = ExpectedState(pc=4)
         e.intregs[1] = 0xffffffffffffffff
         e.intregs[2] = 0x2
-        e.intregs[3] = 0x3
+        e.intregs[3] = 0xfffffffffffffffd
         self.add_case(Program(lst, bigendian), initial_regs, expected=e)
 
     def case_2_absdu(self):
@@ -257,12 +283,12 @@ class AVTestCase(TestAccumulatorBase):
         e = ExpectedState(pc=4)
         e.intregs[1] = 0x2
         e.intregs[2] = 0xffffffffffffffff
-        e.intregs[3] = 0x3
+        e.intregs[3] = 0xfffffffffffffffd
         self.add_case(Program(lst, bigendian), initial_regs, expected=e)
 
-    def case_0_absaddu(self):
-        lst = ["absaddu 3, 1, 2",
-               "absaddu 3, 4, 5",
+    def case_0_absdacu(self):
+        lst = ["absdacu 3, 1, 2",
+               "absdacu 3, 4, 5",
         ]
         lst = list(SVP64Asm(lst, bigendian))
 
@@ -279,9 +305,9 @@ class AVTestCase(TestAccumulatorBase):
         e.intregs[5] = 0x3
         self.add_case(Program(lst, bigendian), initial_regs, expected=e)
 
-    def case_1_absaddu(self):
-        lst = ["absaddu 3, 1, 2",
-               "absaddu 3, 4, 5",
+    def case_1_absdacu(self):
+        lst = ["absdacu 3, 1, 2",
+               "absdacu 3, 4, 5",
         ]
         lst = list(SVP64Asm(lst, bigendian))
 
@@ -298,7 +324,7 @@ class AVTestCase(TestAccumulatorBase):
         e.intregs[5] = 0x3
         self.add_case(Program(lst, bigendian), initial_regs, expected=e)
 
-    def case_2_absaddu(self):
+    def case_2_absdacu(self):
         """weird case where there's a negative number
         * -1 is greater than 2 (as an unsigned number)
           therefore difference is (-1)-(2) which is -3
@@ -312,8 +338,8 @@ class AVTestCase(TestAccumulatorBase):
             =3
         * answer: RT=3
         """
-        lst = ["absaddu 3, 1, 2",
-               "absaddu 3, 4, 5",
+        lst = ["absdacu 3, 1, 2",
+               "absdacu 3, 4, 5",
         ]
         lst = list(SVP64Asm(lst, bigendian))
 
@@ -330,9 +356,9 @@ class AVTestCase(TestAccumulatorBase):
         e.intregs[5] = 0x3
         self.add_case(Program(lst, bigendian), initial_regs, expected=e)
 
-    def case_0_absadds(self):
-        lst = ["absadds 3, 1, 2",
-               "absadds 3, 4, 5",
+    def case_0_absdacs(self):
+        lst = ["absdacs 3, 1, 2",
+               "absdacs 3, 4, 5",
         ]
         lst = list(SVP64Asm(lst, bigendian))
 
@@ -349,13 +375,13 @@ class AVTestCase(TestAccumulatorBase):
         e.intregs[5] = 0x3
         self.add_case(Program(lst, bigendian), initial_regs, expected=e)
 
-    def case_2_absadds(self):
-        """unlike the absaddu weird case, the 0xfff is treated as signed
+    def case_2_absdacs(self):
+        """unlike the absdacu weird case, the 0xfff is treated as signed
         so (2) < (-1) and the difference is (2--1)=3.  next instruction
         adds 6 more.  answer: 9
         """
-        lst = ["absadds 3, 1, 2",
-               "absadds 3, 4, 5",
+        lst = ["absdacs 3, 1, 2",
+               "absdacs 3, 4, 5",
         ]
         lst = list(SVP64Asm(lst, bigendian))
 
@@ -372,3 +398,79 @@ class AVTestCase(TestAccumulatorBase):
         e.intregs[5] = 0x3
         self.add_case(Program(lst, bigendian), initial_regs, expected=e)
 
+    def case_0_cprop(self):
+        lst = ["cprop 3, 1, 2" ]
+        lst = list(SVP64Asm(lst, bigendian))
+        last_pc = len(lst)*4
+        reg_a = 0b000001
+        reg_b = 0b000111
+        reg_t = 0b001111
+
+        initial_regs = [0] * 32
+        initial_regs[1] = reg_a
+        initial_regs[2] = reg_b
+        e = ExpectedState(pc=last_pc)
+        e.intregs[1] = reg_a
+        e.intregs[2] = reg_b
+        e.intregs[3] = reg_t
+        self.add_case(Program(lst, bigendian), initial_regs, expected=e)
+
+    def case_1_cprop(self):
+        lst = ["cprop 3, 1, 2" ]
+        lst = list(SVP64Asm(lst, bigendian))
+        last_pc = len(lst)*4
+        reg_a = 0b000010
+        reg_b = 0b001111
+        reg_t = 0b011100
+
+        initial_regs = [0] * 32
+        initial_regs[1] = reg_a
+        initial_regs[2] = reg_b
+        e = ExpectedState(pc=last_pc)
+        e.intregs[1] = reg_a
+        e.intregs[2] = reg_b
+        e.intregs[3] = reg_t
+        self.add_case(Program(lst, bigendian), initial_regs, expected=e)
+
+    def case_2_cprop(self):
+        lst = ["cprop 3, 1, 2" ]
+        lst = list(SVP64Asm(lst, bigendian))
+        last_pc = len(lst)*4
+        reg_a = 0b000010
+        reg_b = 0b001110
+        reg_t = 0b011110
+
+        initial_regs = [0] * 32
+        initial_regs[1] = reg_a
+        initial_regs[2] = reg_b
+        e = ExpectedState(pc=last_pc)
+        e.intregs[1] = reg_a
+        e.intregs[2] = reg_b
+        e.intregs[3] = reg_t
+        self.add_case(Program(lst, bigendian), initial_regs, expected=e)
+
+    def case_0_bmask(self):
+        """
+        https://git.libre-soc.org/?p=libreriscv.git;a=blob;f=openpower/sv/bmask.py
+        https://git.libre-soc.org/?p=libreriscv.git;a=blob;f=openpower/sv/test_bmask.py
+        https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=openpower/isa/av.mdwn;hb=HEAD
+        SBF = 0b01010 # set before first
+        SOF = 0b01001 # set only first
+        SIF = 0b10000 # set including first 10011 also works no idea why yet
+        """
+        lst = ["bmask 3, 1, 2, 10, 0" ]
+        lst = list(SVP64Asm(lst, bigendian))
+        last_pc = len(lst)*4
+        reg_a = 0b10010100
+        reg_b = 0b11000011
+        reg_t = 0b01000011
+
+        initial_regs = [0] * 32
+        initial_regs[1] = reg_a
+        initial_regs[2] = reg_b
+        e = ExpectedState(pc=last_pc)
+        e.intregs[1] = reg_a
+        e.intregs[2] = reg_b
+        e.intregs[3] = reg_t
+        self.add_case(Program(lst, bigendian), initial_regs, expected=e)
+