switch powmod to using new divmod implementation -- test not enabled yet

[openpower-isa.git] / src / openpower / test / bitmanip / av_cases.py

diff --git a/src/openpower/test/bitmanip/av_cases.py b/src/openpower/test/bitmanip/av_cases.py
index c2ca663d8bb78ade9b4e2f16d9f0a43d3cbaa855..d39e044125814b5a497a52d821077442a6a3cf58 100644 (file)
--- a/src/openpower/test/bitmanip/av_cases.py
+++ b/src/openpower/test/bitmanip/av_cases.py
@@ -1,4 +1,4 @@
-from openpower.sv.trans.svp64 import SVP64Asm
+from openpower.insndb.asm import SVP64Asm
 import random
 from openpower.test.common import TestAccumulatorBase
 from openpower.endian import bigendian
@@ -14,7 +14,7 @@ import unittest
 class AVTestCase(TestAccumulatorBase):
 
     def case_0_maxs(self):
-        lst = ["maxs 3, 1, 2"]
+        lst = ["minmax 3, 1, 2, 3"]
         lst = list(SVP64Asm(lst, bigendian))
 
         initial_regs = [0] * 32
@@ -27,7 +27,7 @@ class AVTestCase(TestAccumulatorBase):
         self.add_case(Program(lst, bigendian), initial_regs, expected=e)
 
     def case_1_maxs(self):
-        lst = ["maxs 3, 1, 2"]
+        lst = ["minmax 3, 1, 2, 3"]
         lst = list(SVP64Asm(lst, bigendian))
 
         initial_regs = [0] * 32
@@ -40,7 +40,7 @@ class AVTestCase(TestAccumulatorBase):
         self.add_case(Program(lst, bigendian), initial_regs, expected=e)
 
     def case_2_maxs_(self):
-        lst = [f"maxs. 3, 1, 2"]
+        lst = [f"minmax. 3, 1, 2, 3"]
         lst = list(SVP64Asm(lst, bigendian))
 
         initial_regs = [0] * 32
@@ -54,7 +54,7 @@ class AVTestCase(TestAccumulatorBase):
         self.add_case(Program(lst, bigendian), initial_regs, expected=e)
 
     def case_3_maxs_(self):
-        lst = [f"maxs. 3, 1, 2"]
+        lst = [f"minmax. 3, 1, 2, 3"]
         lst = list(SVP64Asm(lst, bigendian))
 
         initial_regs = [0] * 32
@@ -64,11 +64,11 @@ class AVTestCase(TestAccumulatorBase):
         e.intregs[1] = 0xc523e996a8ff6215
         e.intregs[2] = 0
         e.intregs[3] = 0
-        e.crregs[0] = 0x2 # RT is zero
+        e.crregs[0] = 0x8 # RB greater (arithmeticslly)
         self.add_case(Program(lst, bigendian), initial_regs, expected=e)
 
     def case_4_maxs_(self):
-        lst = [f"maxs. 3, 1, 2"]
+        lst = [f"minmax. 3, 1, 2, 3"]
         lst = list(SVP64Asm(lst, bigendian))
 
         initial_regs = [0] * 32
@@ -84,7 +84,7 @@ class AVTestCase(TestAccumulatorBase):
     def case_5_maxs_(self):
         """max negative number compared against +ve number
         """
-        lst = [f"maxs. 3, 1, 2"]
+        lst = [f"minmax. 3, 1, 2, 3"]
         lst = list(SVP64Asm(lst, bigendian))
 
         initial_regs = [0] * 32
@@ -97,8 +97,22 @@ class AVTestCase(TestAccumulatorBase):
         e.crregs[0] = 0x4 # RT is +ve
         self.add_case(Program(lst, bigendian), initial_regs, expected=e)
 
+    def case_6_maxs_(self):
+        lst = [f"minmax. 3, 1, 2, 3"]
+        lst = list(SVP64Asm(lst, bigendian))
+
+        initial_regs = [0] * 32
+        initial_regs[1] = 0x8000_0000_0000_0000
+        initial_regs[2] = 0x8000_0000_0000_0000
+        e = ExpectedState(pc=4)
+        e.intregs[1] = 0x8000_0000_0000_0000
+        e.intregs[2] = 0x8000_0000_0000_0000
+        e.intregs[3] = 0x8000_0000_0000_0000
+        e.crregs[0] = 0x2 # values are equal
+        self.add_case(Program(lst, bigendian), initial_regs, expected=e)
+
     def case_0_mins(self):
-        lst = ["mins 3, 1, 2"]
+        lst = ["minmax 3, 1, 2, 2"]
         lst = list(SVP64Asm(lst, bigendian))
 
         initial_regs = [0] * 32
@@ -111,7 +125,7 @@ class AVTestCase(TestAccumulatorBase):
         self.add_case(Program(lst, bigendian), initial_regs, expected=e)
 
     def case_2_mins_(self):
-        lst = [f"mins. 3, 1, 2"]
+        lst = [f"minmax. 3, 1, 2, 2"]
         lst = list(SVP64Asm(lst, bigendian))
 
         initial_regs = [0] * 32
@@ -127,7 +141,7 @@ class AVTestCase(TestAccumulatorBase):
     def case_5_mins_(self):
         """min negative number compared against +ve number
         """
-        lst = [f"mins. 3, 1, 2"]
+        lst = [f"minmax. 3, 1, 2, 2"]
         lst = list(SVP64Asm(lst, bigendian))
 
         initial_regs = [0] * 32
@@ -137,11 +151,11 @@ class AVTestCase(TestAccumulatorBase):
         e.intregs[1] = 1
         e.intregs[2] = 0x8000_0000_0000_0000
         e.intregs[3] = 0x8000_0000_0000_0000
-        e.crregs[0] = 0x8 # RT is -ve
+        e.crregs[0] = 0x4  # r1 >s r2
         self.add_case(Program(lst, bigendian), initial_regs, expected=e)
 
     def case_0_maxu(self):
-        lst = ["maxu 3, 1, 2"]
+        lst = ["minmax 3, 1, 2, 1"]
         lst = list(SVP64Asm(lst, bigendian))
 
         initial_regs = [0] * 32
@@ -156,7 +170,7 @@ class AVTestCase(TestAccumulatorBase):
     def case_5_minu_(self):
         """min +ve numbers
         """
-        lst = [f"minu. 3, 1, 2"]
+        lst = [f"minmax. 3, 1, 2, 0"]
         lst = list(SVP64Asm(lst, bigendian))
 
         initial_regs = [0] * 32
@@ -166,7 +180,7 @@ class AVTestCase(TestAccumulatorBase):
         e.intregs[1] = 1
         e.intregs[2] = 0x8000_0000_0000_0000
         e.intregs[3] = min(e.intregs[1], e.intregs[2])
-        e.crregs[0] = 0x4
+        e.crregs[0] = 0x8  # r1 <u r2
         self.add_case(Program(lst, bigendian), initial_regs, expected=e)
 
     def case_0_avgadd(self):
@@ -489,18 +503,18 @@ class AVTestCase(TestAccumulatorBase):
         NOTE: the numbering above for bm[] is in *MSB0* order.
         """
  
-        lst = ["bmask 3, 1, 2,  3, 0", # OR  : RA | (RA-1)
-               "bmask 4, 1, 2, 11, 0", # AND : RA & (RA-1)
-               "bmask 5, 1, 2, 19, 0", # XOR : RA ^ (RA-1)
+        lst = ["bmask 3, 1, 2,  3, 0", # OR  : RA | (RA-1) 00 01 1
+               "bmask 4, 1, 2, 11, 0", # AND : RA & (RA-1) 01 01 1
+               "bmask 5, 1, 2, 19, 0", # XOR : RA ^ (RA-1) 10 01 1
                "bmask 6, 1, 2, 27, 0", # 0   : 0
               ]
         lst = list(SVP64Asm(lst, bigendian))
         last_pc = len(lst)*4
         reg_a =  0b10010100
         reg_b =  0b11000011
-        reg_t0 = 0b10010111
-        reg_t1 = 0b10010000
-        reg_t2 = 0b00000111
+        reg_t0 = 0b11000011
+        reg_t1 = 0b00000000
+        reg_t2 = 0b11000011
         reg_t3 = 0b00000000
 
         initial_regs = [0] * 32
@@ -514,3 +528,56 @@ class AVTestCase(TestAccumulatorBase):
         e.intregs[5] = reg_t2
         e.intregs[6] = reg_t3
         self.add_case(Program(lst, bigendian), initial_regs, expected=e)
+
+    def case_2_bmask(self):
+        """
+        SBF = 0b01010 # set before first
+        SOF = 0b01001 # set only first
+        SIF = 0b10000 # set including first 10011 also works no idea why yet
+        """
+        #SIF
+        lst = ["bmask 3, 1, 2, 16, 0",]
+              # "bmask 6, 4, 5, 16, 0",
+              # "bmask 9, 7, 8, 16, 0",
+              # "bmask 12, 10, 11, 16, 0",
+              #]
+        lst = list(SVP64Asm(lst, bigendian))
+        last_pc = len(lst)*4
+
+        initial_regs = [0] * 32
+        e = ExpectedState(pc=last_pc)
+
+        m  = 0b11000011
+        v3 = 0b10010100 # vmsif.m v2, v3
+        v2 = 0b11000011 # v2
+        initial_regs[1] = v3
+        initial_regs[2] = m
+        e.intregs[1] = v3
+        e.intregs[2] = m
+        e.intregs[3] = v2
+
+        self.add_case(Program(lst, bigendian), initial_regs, expected=e)
+
+    def case_3_bmask(self):
+        """
+        SBF = 0b01010 # set before first
+        SOF = 0b01001 # set only first
+        SIF = 0b10000 # set including first 10011 also works no idea why yet
+        """
+        #SOF
+        lst = ["bmask 3, 1, 2, 9, 0",]
+        lst = list(SVP64Asm(lst, bigendian))
+        last_pc = len(lst)*4
+
+        initial_regs = [0] * 32
+        e = ExpectedState(pc=last_pc)
+
+        m  = 0b11000011
+        v3 = 0b11010100 # vmsof.m v2, v3
+        v2 = 0b01000000 # v2
+        initial_regs[1] = v3
+        initial_regs[2] = m
+        e.intregs[1] = v3
+        e.intregs[2] = m
+        e.intregs[3] = v2
+        self.add_case(Program(lst, bigendian), initial_regs, expected=e)