working on svp64 utf-8 validation -- still broken

[openpower-isa.git] / src / openpower / test / runner.py

diff --git a/src/openpower/test/runner.py b/src/openpower/test/runner.py
index 55f2f3727a86eab14a6f4d407fee7c054d3a071d..b03509b1f10bf59986683f0a7ab7cef5c3628536 100644 (file)
--- a/src/openpower/test/runner.py
+++ b/src/openpower/test/runner.py
@@ -1,3 +1,4 @@
+# SPDX-License-Identifier: LGPL-2-or-later
 """TestRunner class, part of the Test API
 
 SPDX-License: LGPLv2+
@@ -115,13 +116,14 @@ class TestRunnerBase(FHDLTestCase):
     """
     def __init__(self, tst_data, microwatt_mmu=False, rom=None,
                         svp64=True, run_hdl=None, run_sim=True,
-                        allow_overlap=False):
+                        allow_overlap=False, inorder=False):
         super().__init__("run_all")
         self.test_data = tst_data
         self.microwatt_mmu = microwatt_mmu
         self.rom = rom
         self.svp64 = svp64
         self.allow_overlap = allow_overlap
+        self.inorder = inorder
         self.run_hdl = run_hdl
         self.run_sim = run_sim
 
@@ -142,8 +144,9 @@ class TestRunnerBase(FHDLTestCase):
 
         pspec = TestMemPspec(ldst_ifacetype=ldst_ifacetype,
                              imem_ifacetype=imem_ifacetype,
-                             addr_wid=48,
+                             addr_wid=64,
                              mask_wid=8,
+                             XLEN=64,
                              imem_reg_wid=64,
                              # wb_data_width=32,
                              use_pll=False,
@@ -154,6 +157,7 @@ class TestRunnerBase(FHDLTestCase):
                              core_domain="sync", # no alternative domain
                              svp64=self.svp64,
                              allow_overlap=self.allow_overlap,
+                             inorder=self.inorder,
                              mmu=self.microwatt_mmu,
                              reg_wid=64)
 
@@ -200,8 +204,7 @@ class TestRunnerBase(FHDLTestCase):
             # get each test, completely reset the core, and run it
 
             for test in self.test_data:
-
-                with self.subTest(test.name):
+                with self.subTest(test.name, **test.subtest_args):
 
                     ###### PREPARATION PHASE AT START OF TEST #######
 
@@ -496,6 +499,7 @@ class TestRunnerBase(FHDLTestCase):
 
         # optionally, if a wishbone-based ROM is passed in, run that as an
         # extra emulated process
+        self.default_mem = {}
         if self.rom is not None:
             print ("TestRunner with MMU ROM")
             pprint (self.rom)