working on svp64 utf-8 validation -- still broken

[openpower-isa.git] / src / openpower / test / runner.py

diff --git a/src/openpower/test/runner.py b/src/openpower/test/runner.py
index fd6540253b85c1cddd92af317487193ba59ec076..b03509b1f10bf59986683f0a7ab7cef5c3628536 100644 (file)
--- a/src/openpower/test/runner.py
+++ b/src/openpower/test/runner.py
@@ -1,3 +1,4 @@
+# SPDX-License-Identifier: LGPL-2-or-later
 """TestRunner class, part of the Test API
 
 SPDX-License: LGPLv2+
@@ -15,7 +16,7 @@ related bugs:
 """
 
 from nmigen import Module, ClockSignal
-from copy import copy
+from copy import copy, deepcopy
 from pprint import pprint
 
 # NOTE: to use cxxsim, export NMIGEN_SIM_MODE=cxxsim from the shell
@@ -32,6 +33,7 @@ from openpower.decoder.power_decoder2 import PowerDecode2
 from soc.config.test.test_loadstore import TestMemPspec
 from nmutil.util import wrap
 from openpower.test.wb_get import wb_get
+import openpower.test.wb_get as wbget
 from openpower.test.state import TestState, StateRunner, ExpectedState
 
 
@@ -114,13 +116,14 @@ class TestRunnerBase(FHDLTestCase):
     """
     def __init__(self, tst_data, microwatt_mmu=False, rom=None,
                         svp64=True, run_hdl=None, run_sim=True,
-                        allow_overlap=False):
+                        allow_overlap=False, inorder=False):
         super().__init__("run_all")
         self.test_data = tst_data
         self.microwatt_mmu = microwatt_mmu
         self.rom = rom
         self.svp64 = svp64
         self.allow_overlap = allow_overlap
+        self.inorder = inorder
         self.run_hdl = run_hdl
         self.run_sim = run_sim
 
@@ -141,8 +144,9 @@ class TestRunnerBase(FHDLTestCase):
 
         pspec = TestMemPspec(ldst_ifacetype=ldst_ifacetype,
                              imem_ifacetype=imem_ifacetype,
-                             addr_wid=48,
+                             addr_wid=64,
                              mask_wid=8,
+                             XLEN=64,
                              imem_reg_wid=64,
                              # wb_data_width=32,
                              use_pll=False,
@@ -150,8 +154,10 @@ class TestRunnerBase(FHDLTestCase):
                              xics=False,
                              gpio=False,
                              regreduce=not self.allow_overlap,
+                             core_domain="sync", # no alternative domain
                              svp64=self.svp64,
                              allow_overlap=self.allow_overlap,
+                             inorder=self.inorder,
                              mmu=self.microwatt_mmu,
                              reg_wid=64)
 
@@ -161,6 +167,10 @@ class TestRunnerBase(FHDLTestCase):
         # The methods contained in the respective Runner classes are
         # called using this list when possible
 
+        # allow wb_get to run
+        if self.rom is not None:
+            wbget.stop = False
+
         state_list = []
 
         if self.run_hdl:
@@ -176,6 +186,8 @@ class TestRunnerBase(FHDLTestCase):
         # but Simulation-only fails without it
         intclk = ClockSignal("coresync")
         comb += intclk.eq(ClockSignal())
+        dbgclk = ClockSignal("dbgsync")
+        comb += dbgclk.eq(ClockSignal())
 
         # nmigen Simulation - everything runs around this, so it
         # still has to be created.
@@ -192,11 +204,20 @@ class TestRunnerBase(FHDLTestCase):
             # get each test, completely reset the core, and run it
 
             for test in self.test_data:
-
-                with self.subTest(test.name):
+                with self.subTest(test.name, **test.subtest_args):
 
                     ###### PREPARATION PHASE AT START OF TEST #######
 
+                    # HACK: if there is test memory and wb_get is in use,
+                    # overwrite (reset) the wb_get memory dictionary with
+                    # the test's memory contents (oh, and put the wb_get
+                    # memory back in as well)
+                    self.default_mem.clear()
+                    if self.rom is not None:
+                        self.default_mem.update(deepcopy(self.rom))
+                    if test.mem is not None:
+                        self.default_mem.update(deepcopy(test.mem))
+
                     for runner in state_list:
                         yield from runner.prepare_for_test(test)
 
@@ -298,9 +319,13 @@ class TestRunnerBase(FHDLTestCase):
                         # do actual comparison, against last item
                         last_sim.compare(test.expected)
 
+                    # check number of instructions run (sanity)
                     if self.run_hdl and self.run_sim:
-                        self.assertTrue(len(hdl_states) == len(sim_states),
-                                    "number of instructions run not the same")
+                        n_hdl = len(hdl_states)
+                        n_sim = len(sim_states)
+                        self.assertTrue(n_hdl == n_sim,
+                                    "number of instructions %d %d "
+                                    "run not the same" % (n_hdl, n_sim))
 
                 ###### END OF A TEST #######
                 # StateRunner.end_test()
@@ -314,6 +339,10 @@ class TestRunnerBase(FHDLTestCase):
             for runner in state_list:
                 yield from runner.cleanup() # TODO, some arguments?
 
+            # finally stop wb_get from going
+            if self.rom is not None:
+                wbget.stop = True
+
         styles = {
             'dec': {'base': 'dec'},
             'bin': {'base': 'bin'},
@@ -453,8 +482,12 @@ class TestRunnerBase(FHDLTestCase):
                 'core.l0.pimem.bus__dat_we',
             ]
 
-        write_gtkw("issuer_simulator.gtkw",
-                   "issuer_simulator.vcd",
+        gtkname = "issuer_simulator"
+        if self.rom:
+            gtkname += "_mmu"
+
+        write_gtkw("%s.gtkw" % gtkname,
+                   "%s.vcd" % gtkname,
                    traces, styles, module='top.issuer')
 
         # add run of instructions
@@ -466,16 +499,17 @@ class TestRunnerBase(FHDLTestCase):
 
         # optionally, if a wishbone-based ROM is passed in, run that as an
         # extra emulated process
+        self.default_mem = {}
         if self.rom is not None:
             print ("TestRunner with MMU ROM")
             pprint (self.rom)
             dcache = hdlrun.issuer.core.fus.fus["mmu0"].alu.dcache
             icache = hdlrun.issuer.core.fus.fus["mmu0"].alu.icache
-            default_mem = self.rom
+            self.default_mem = deepcopy(self.rom)
             sim.add_sync_process(wrap(wb_get(dcache.bus,
-                                             default_mem, "DCACHE")))
+                                             self.default_mem, "DCACHE")))
             sim.add_sync_process(wrap(wb_get(icache.ibus,
-                                             default_mem, "ICACHE")))
+                                             self.default_mem, "ICACHE")))
 
-        with sim.write_vcd("issuer_simulator.vcd"):
+        with sim.write_vcd("%s.vcd" % gtkname):
             sim.run()